new-sonar/firmware/src/eth.rs

//! Smoltcp ethernet driver for LiteETH instance.
//!
//! Much of the code and implementation ideas are stolen from https://docs.tockos.org/src/litex/liteeth.rs.html#1-307

// God I hate how there's 0 documentation for LiteEth. No explanation of all the
// registers or anything, just here's a bunch of things, you've got to look at
// the gateware to figure out how it works.

// Some notes I'm not too sure where to put:
// - The SRAM writer (i.e. RX DMA) must have the event cleared to mark the slot as ready
// - Do the event registers change with the selected slot? I don't think so. So how
//   are you supposed to know which RX slot to use? In this case I only use one, so I'm
//   not going to care, but it's not obvious.
// - Slots are sized to ethernet MTU (1530), and addressed by the closest log2
//   thing, so 2048 bytes each

const LITEETH_BASE: u32 = 0x0300_0000;

const CTRL_RESET: u32 = 0x000;
const CTRL_SCRATCH: u32 = 0x004;

// Writer, or RX register blocks
const ETHMAC_SRAM_WRITER_SLOT: u32 = 0x800;
const ETHMAC_SRAM_WRITER_LENGTH: u32 = 0x804;
const ETHMAC_SRAM_WRITER_EV_STATUS: u32 = 0x80c;
const ETHMAC_SRAM_WRITER_EV_PENDING: u32 = 0x810;
const ETHMAC_SRAM_WRITER_EV_ENABLE: u32 = 0x814;

// Reader, or TX register blocks
const ETHMAC_SRAM_READER_START: u32 = 0x818;
const ETHMAC_SRAM_READER_READY: u32 = 0x81c;
const ETHMAC_SRAM_READER_SLOT: u32 = 0x824;
const ETHMAC_SRAM_READER_LENGTH: u32 = 0x828;
const ETHMAC_SRAM_READER_EV_STATUS: u32 = 0x82c;
const ETHMAC_SRAM_READER_EV_PENDING: u32 = 0x830;
const ETHMAC_SRAM_READER_EV_ENABLE: u32 = 0x834;

const NUM_RX_SLOTS: u32 = 2;
const NUM_TX_SLOTS: u32 = 2;
const MTU: usize = 1530;

use crate::{busy_wait, read_reg, write_reg};

pub struct LiteEthDevice {
    base_addr: u32,
}

pub struct LiteEthTxToken {
    pub base_addr: u32,
    pub slot: u32,
}

pub struct LiteEthRxToken {
    pub base_addr: u32,
}

impl LiteEthDevice {
    /// Initialises the device and returns an instance. Unsafe because there are
    /// no checks for other users.
    pub unsafe fn try_init(base_addr: u32) -> Option<Self> {
        if !LiteEthDevice::check_wishbone_access(base_addr) {
            return None;
        }
        // Reset liteeth
        write_reg(base_addr + CTRL_RESET, 1u32);
        busy_wait(200);
        write_reg(base_addr + CTRL_RESET, 0u32);
        busy_wait(200);

        // Set up RX slot 0
        write_reg(base_addr + ETHMAC_SRAM_WRITER_SLOT, 0);
        // Clear to mark the slot as available
        write_reg(base_addr + ETHMAC_SRAM_WRITER_EV_PENDING, 1u32);

        // Clear TX event (unsure if necessary)
        write_reg(base_addr + ETHMAC_SRAM_READER_EV_PENDING, 1u32);

        // Disable event interrupts, we poll, so no use for an interrupt
        write_reg(base_addr + ETHMAC_SRAM_READER_EV_ENABLE, 0u32);
        write_reg(base_addr + ETHMAC_SRAM_WRITER_EV_ENABLE, 0u32);

        // Return a new device
        Some(Self { base_addr })
    }

    /// Checks that wishbone memory access is correct for the given base address
    unsafe fn check_wishbone_access(base_addr: u32) -> bool {
        // Read scratch register, which resets to 0x12345678
        let value: u32 = read_reg(base_addr + CTRL_SCRATCH);

        // If this isn't true, we screwed.
        return value == 0x12345678;
    }
}

impl smoltcp::phy::Device for LiteEthDevice {
    type RxToken<'a> = LiteEthRxToken;
    type TxToken<'a> = LiteEthTxToken;

    fn receive(
        &mut self,
        _timestamp: smoltcp::time::Instant,
    ) -> Option<(Self::RxToken<'_>, Self::TxToken<'_>)> {
        // Check if available, if so , return a RxToken + a TxToken to slot 1

        unsafe {
            if read_reg::<u32>(self.base_addr + ETHMAC_SRAM_WRITER_EV_STATUS) == 0 {
                // No data is available in writer slot 0
                return None;
            }

            // Check if TX slot 1 is available for the "return" packet
            write_reg(self.base_addr + ETHMAC_SRAM_READER_SLOT, 1u32);
            if read_reg::<u32>(self.base_addr + ETHMAC_SRAM_READER_READY) != 1 {
                return None;
            }

            // We have data, and TX slot 1 is ready for something to be potentially transmitted,
            // so we can return valid tokens
            Some((
                LiteEthRxToken {
                    base_addr: self.base_addr,
                },
                LiteEthTxToken {
                    base_addr: self.base_addr,
                    slot: 1,
                },
            ))
        }
    }

    fn transmit(&mut self, _timestamp: smoltcp::time::Instant) -> Option<Self::TxToken<'_>> {
        // Check if slot 0 is ready, if so, return TxToken to slot 0
        unsafe {
            write_reg(self.base_addr + ETHMAC_SRAM_READER_SLOT, 0u32);
            if read_reg::<u32>(self.base_addr + ETHMAC_SRAM_READER_READY) == 0 {
                return None;
            }
        }

        Some(LiteEthTxToken {
            base_addr: self.base_addr,
            slot: 0,
        })
    }

    fn capabilities(&self) -> smoltcp::phy::DeviceCapabilities {
        use smoltcp::phy::*;
        let mut caps = DeviceCapabilities::default();
        caps.medium = Medium::Ethernet;
        caps.max_transmission_unit = MTU;
        caps.max_burst_size = Some(MTU);

        caps
    }
}

impl smoltcp::phy::TxToken for LiteEthTxToken {
    fn consume<R, F>(self, len: usize, f: F) -> R
    where
        F: FnOnce(&mut [u8]) -> R,
    {
        let tx_slot_base: u32 = self.base_addr + NUM_RX_SLOTS * 2048;
        let tx_slot_addr = tx_slot_base + (self.slot as u32) * 2048;
        let tx_slot: &mut [u8] =
            unsafe { core::slice::from_raw_parts_mut(tx_slot_addr as *mut u8, MTU) };

        // Write data to buffer
        let res = f(tx_slot);

        // Write length, and start sending data
        unsafe {
            // set slot
            write_reg(self.base_addr + ETHMAC_SRAM_READER_SLOT, self.slot);
            // set length
            write_reg(self.base_addr + ETHMAC_SRAM_READER_LENGTH, len as u32);
            // send data
            write_reg(self.base_addr + ETHMAC_SRAM_READER_START, 1u32);
        }

        res
    }
}

impl smoltcp::phy::RxToken for LiteEthRxToken {
    fn consume<R, F>(self, f: F) -> R
    where
        F: FnOnce(&mut [u8]) -> R,
    {
        let len = unsafe {
            // Select slot 0
            write_reg(self.base_addr + ETHMAC_SRAM_WRITER_SLOT, 0u32);
            // Read the available length
            read_reg::<u32>(self.base_addr + ETHMAC_SRAM_READER_LENGTH)
        };

        let rx_slot_addr: u32 = self.base_addr + 2048;
        let rx_slot: &mut [u8] =
            unsafe { core::slice::from_raw_parts_mut(rx_slot_addr as *mut u8, len as usize) };

        // Read data from buffer
        let res = f(rx_slot);

        // Clear event to mark slot as available
        unsafe {
            write_reg(self.base_addr + ETHMAC_SRAM_WRITER_EV_PENDING, 1u32);
        }

        res
    }
}