David Lenfesty
26389576d5
Unsure if this is working, not sure if I have the tools to even know if it does. I could spend the time to actually write the packet by hand, or I could probably spend ~2x the time and get smoltcp up. Either way, the HW is validated, I am bringing up a link, I can talk to LiteEth, so past here is driver stuff
85 lines
2.5 KiB
Rust
85 lines
2.5 KiB
Rust
//! Quick and hacky ethernet thing to test
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const LITEETH_BASE: u32 = 0x0200_0000;
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const ETHMAC_SRAM_WRITER_EV_PENDING: u32 = LITEETH_BASE + 0x810;
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const ETHMAC_SRAM_WRITER_EV_ENABLE: u32 = LITEETH_BASE + 0x814;
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const ETHMAC_SRAM_READER_EV_PENDING: u32 = LITEETH_BASE + 0x830;
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const ETHMAC_SRAM_READER_EV_ENABLE: u32 = LITEETH_BASE + 0x834;
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// OMFG, READER is TX, WRITER is RX
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const ETHMAC_SRAM_READER_SLOT: u32 = LITEETH_BASE + 0x824;
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const ETHMAC_SRAM_READER_LENGTH: u32 = LITEETH_BASE + 0x828;
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const ETHMAC_SRAM_READER_START: u32 = LITEETH_BASE + 0x818;
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const ETHMAC_SRAM_READER_READY: u32 = LITEETH_BASE + 0x81c;
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fn write_u32_reg(addr: u32, value: u32) {
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use core::ptr::write;
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unsafe {
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write(addr as *mut u32, value);
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}
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}
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fn read_u32_reg(addr: u32) -> u32 {
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use core::ptr::read;
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unsafe {
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return read(addr as *mut u32);
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}
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}
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pub fn is_wishbone_correct() -> bool {
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let value = read_u32_reg(LITEETH_BASE + 4);
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// If this isn't true, we screwed.
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return value == 0x12345678;
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}
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pub fn init() {
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// Clear any potential pending events
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write_u32_reg(ETHMAC_SRAM_WRITER_EV_PENDING, 1);
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write_u32_reg(ETHMAC_SRAM_READER_EV_PENDING, 1);
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// Disable all events
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write_u32_reg(ETHMAC_SRAM_WRITER_EV_ENABLE, 0);
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write_u32_reg(ETHMAC_SRAM_READER_EV_ENABLE, 0);
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}
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// a8:a1:59:32:a7:a5
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const ares_mac: [u8; 6] = [0xA8, 0xA1, 0x59, 0x32, 0xA7, 0xA5];
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const fake_mac: [u8; 6] = [0x00, 0x01, 0x02, 0x03, 0x04, 0x05];
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/// Just make an ethernet frame and yeet it
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pub fn tranmsit() {
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// Preamble/start delimiter/crc are all handled for us by the MAC
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let frame: [u8; 18] = [
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// TODO endianness of MAC addresses?
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0xA8, 0xA1, 0x59, 0x32, 0xA7, 0xA5, // Destination MAC (ares)
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0x00, 0x01, 0x02, 0x03, 0x04, 0x05, // Source MAC (fake)
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0x08, 0x00, // Ethertype frame
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0xDE, 0xAD, 0xBE, 0xEF, // Data!
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];
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// buffer_depth = 2048
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// it goes, base, RX slot 0, RX slot ..., Tx slot 0, tx slot ...,
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const TX_SLOT_LOC: u32 = LITEETH_BASE + 1 * 2048;
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let tx_slot: &mut [u8] = unsafe {
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core::slice::from_raw_parts_mut(TX_SLOT_LOC as *mut u8, 2048)
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};
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// Copy our frame into the slot buffer
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tx_slot[..18].copy_from_slice(&frame);
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// Set slot and packet length
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write_u32_reg(ETHMAC_SRAM_READER_SLOT, 0);
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write_u32_reg(ETHMAC_SRAM_READER_LENGTH, 18);
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// Wait to be ready
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while read_u32_reg(ETHMAC_SRAM_READER_READY) == 0 {}
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// Write!
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write_u32_reg(ETHMAC_SRAM_READER_START, 1);
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}
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