David Lenfesty
8d00e15835
Bus widths should now all be correct. (addresses and sizes in amaranth take into account the granularity selection, so granularity acts like two extra bits on the bus address line) Also don't ignore a warning about undriven resets. Turns out that can gate *everything* off in your design.
92 lines
3.1 KiB
Python
92 lines
3.1 KiB
Python
from amaranth import *
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from amaranth.lib.io import pin_layout
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from amaranth_soc.wishbone.bus import Interface
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from amaranth_soc.memory import MemoryMap
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__all__ = ["LiteEth", "rgmii_layout"]
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# TODO maybe this should just call liteeth_gen to close the loop?
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class LiteEth(Elaboratable, Interface):
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def __init__(self, eth_interface):
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self.eth_interface = eth_interface
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# Addr width is 13 bits to accomodate 0x1FFF, which is well past what we care about
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Interface.__init__(self, addr_width=15, data_width=32, granularity=8, features=["cti", "bte", "err"])
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# TODO I need to understand the semantics here better
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memory_map = MemoryMap(addr_width=17, data_width=8)
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#memory_map.add_resource(self, name="LiteETH", size=0x2000)
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self.memory_map = memory_map
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self.interrupt = Signal()
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# TODO this really shouldn't technically happen here, because we can elaborate one module multiple times,
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# but since I use it once it isn't actually a problem.
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def elaborate(self, platform):
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if platform is not None:
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platform.add_file("liteeth_core.v", open("liteeth/gateware/liteeth_core.v", 'r').read())
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m = Module()
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# TODO I have to provide TX/RX clocks myself
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core = Instance(
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"liteeth_core",
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i_sys_clock=ClockSignal(),
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i_sys_reset=Const(0),
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# RGMII signals
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o_rgmii_eth_clocks_tx=self.eth_interface.tx_clk,
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i_rgmii_eth_clocks_rx=self.eth_interface.rx_clk,
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o_rgmii_eth_rst_n=self.eth_interface.rst,
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i_rgmii_eth_int_n=Const(1),
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# TODO actually fix the platform to support this problem.
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#i_rgmii_eth_mdio=self.eth_interface.mdio,
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o_rgmii_eth_mdc=self.eth_interface.mdc,
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i_rgmii_eth_rx_ctl=self.eth_interface.rx_ctl,
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i_rgmii_eth_rx_data=self.eth_interface.rx_data,
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o_rgmii_eth_tx_ctl=self.eth_interface.tx_ctl,
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o_rgmii_eth_tx_data=self.eth_interface.tx_data,
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# Wishbone all the things
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i_wishbone_adr=self.adr,
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i_wishbone_dat_w=self.dat_w,
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o_wishbone_dat_r=self.dat_r,
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i_wishbone_sel=self.sel,
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i_wishbone_cyc=self.cyc,
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i_wishbone_stb=self.stb,
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o_wishbone_ack=self.ack,
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i_wishbone_we=self.we,
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i_wishbone_cti=self.cti,
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i_wishbone_bte=self.bte,
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o_wishbone_err=self.err,
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o_interrupt=self.interrupt,
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)
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# TODO connect ethernet interface
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m.submodules.core = core
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return m
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rgmii_layout = [
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("tx_clk", pin_layout(1, "o")),
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("rx_clk", pin_layout(1, "i")),
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("rst", pin_layout(1, "o")),
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("int_n", pin_layout(1, "i")),
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# TODO is this not IO? why does LiteEth say input?
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# I think the answer is it uses a primitive, not 100% right now
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("mdio", pin_layout(1, "i")),
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("mdc", pin_layout(1, "o")),
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("rx_ctl", pin_layout(1, "i")),
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("rx_data", pin_layout(4, "i")),
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("tx_ctl", pin_layout(1, "o")),
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("tx_data", pin_layout(4, "o")),
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]
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