191 lines
4.6 KiB
Rust
191 lines
4.6 KiB
Rust
#![no_std]
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#![no_main]
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// TODO remove
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#![allow(unused)]
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extern crate panic_halt;
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use core::fmt::Write;
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use core::{
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arch::asm,
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ptr::{read_volatile, write_volatile},
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};
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use embedded_hal::prelude::{_embedded_hal_blocking_i2c_Read, _embedded_hal_blocking_i2c_Write};
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use mcp4726::Status;
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use riscv_rt::entry;
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use smoltcp::wire::{IpAddress, Ipv4Address};
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use smoltcp::{
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iface::{SocketSet, SocketStorage},
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time::Instant,
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wire::HardwareAddress,
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};
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mod eth;
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mod i2c;
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mod mcp4726;
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mod uart;
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mod litex_uart;
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mod logging;
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const MAC: [u8; 6] = [0xA0, 0xBB, 0xCC, 0xDD, 0xEE, 0xF0];
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static mut SECONDS: u32 = 0;
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/// External interrupt handler
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#[export_name = "MachineExternal"]
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fn external_interrupt_handler() {
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let cause = riscv::register::mcause::read();
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let mut uart = litex_uart::LiteXUart::new(0xf000_4000);
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writeln!(uart, "mcause: {}", cause.bits());
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if (cause.is_interrupt()) {
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let mut uart = litex_uart::LiteXUart::new(0xf000_4000);
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writeln!(uart, "mcause: {}", cause.code());
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if cause.code() == 1 {
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// TIMER0 event, we have reset so count another second
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}
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}
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}
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// use `main` as the entry point of this application
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// `main` is not allowed to return
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#[entry]
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fn main() -> ! {
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//unsafe { eth::init(); }
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//let blink_period = unsafe {
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// if eth::is_wishbone_correct() {
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// 10_000_000
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// } else {
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// 500_000
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// }
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//};
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let blink_period = 10_000_000u32;
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let mut uart = litex_uart::LiteXUart::new(0xf000_4000);
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writeln!(uart, "uart init");
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// enable timer
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let mut device = unsafe { eth::LiteEthDevice::try_init(0xf000_0800, 0x8000_0000).unwrap() };
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writeln!(uart, "eth init");
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use smoltcp::wire::{EthernetAddress, HardwareAddress};
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let mut config = smoltcp::iface::Config::default();
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config.hardware_addr = Some(HardwareAddress::Ethernet(EthernetAddress::from_bytes(&MAC)));
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let mut iface = smoltcp::iface::Interface::new(config, &mut device);
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// Set address
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iface.update_ip_addrs(|ip_addrs| {
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ip_addrs
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.push(smoltcp::wire::IpCidr::new(
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IpAddress::Ipv4(Ipv4Address::new(192, 168, 88, 69)),
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24,
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))
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.unwrap();
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});
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iface
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.routes_mut()
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.add_default_ipv4_route(Ipv4Address::new(192, 168, 88, 1))
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.unwrap();
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// Create socket set with 4 available
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let mut socket_storage = [SocketStorage::EMPTY; 4];
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let mut socket_set = SocketSet::new(&mut socket_storage[..]);
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let mut last_blink: u32 = 0;
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let mut toggle = false;
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//defmt::info!("Done setup");
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unsafe {
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//riscv::interrupt::enable();
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//riscv::register::mie::set_mext();
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//riscv::register::mie::set_msoft();
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// Enable UART rx event for test
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//write_reg(0xf000_4014, 1u32);
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// Timer stuff
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write_reg(0xf000_3808, 0u32); // Disable timer
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write_reg(0xf000_3800, 0u32); // Set LOAD value
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write_reg(0xf000_3804, 60_000_000u32); // Set RELOAD value
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write_reg(0xf000_3808, 1u32); // Enable timer
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// Enable timer event
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//write_reg(0xf000_381c, 1u32);
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}
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loop {
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let now = millis();
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if now - last_blink > 1000 {
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last_blink = now;
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toggle = !toggle;
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write_led(if toggle { 1 } else { 0 });
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let val: u32 = unsafe {read_reg(0x8000_2000)};
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writeln!(uart, "Sampler value: 0x{:08x}", val).unwrap();
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}
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if iface.poll(Instant::from_millis(now), &mut device, &mut socket_set) {
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}
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handle_timer_event();
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}
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}
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fn handle_timer_event() {
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unsafe {
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if read_reg::<u32>(0xf000_3818) == 0 {
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return;
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}
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// Clear TIMER0 event status, and update time
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write_reg(0xf000_3818, 1u32);
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SECONDS += 1;
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}
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}
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fn busy_wait(ms: u32) {
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//let start = millis();
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//while millis() - start < ms {
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// unsafe {
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// asm!("nop");
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// }
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//}
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for i in 0..ms*20_000 {
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unsafe {asm!("nop");}
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}
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}
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fn write_led(val: u32) {
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unsafe {
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write_reg(0xf000_2000, val);
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}
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}
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unsafe fn write_reg<T>(addr: u32, value: T) {
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write_volatile(addr as *mut T, value);
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}
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unsafe fn read_reg<T>(addr: u32) -> T {
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return read_volatile(addr as *mut T);
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}
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fn millis() -> u32 {
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riscv::interrupt::free(|| {
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unsafe {
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// Latch timer value
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write_reg(0xf000_380c, 1u32);
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// Read timer value
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let val: u32 = read_reg(0xf000_3810);
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let val = 60_000_000 - val;
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(SECONDS * 1000) + val / 60_000
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}
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})
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}
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