David Lenfesty
490b92b1fd
Basic details seem to be working, and I'm on my way with testing. Next steps: - Build out more local testing utilities - Build out unittest infrastructure - Flesh out more tests to verify operation
251 lines
7.9 KiB
Python
251 lines
7.9 KiB
Python
from amaranth import *
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from amaranth.lib.coding import PriorityEncoder
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from amaranth_soc.csr import *
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from amaranth_soc.memory import *
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from amlib.io.i2c import I2CInitiator, I2CTarget
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from amaranth.sim import *
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from math import floor, log2, ceil
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class I2C(Elaboratable):
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"""
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CSR-based I2C master peripheral.
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Based on the amlib I2CInitiator, simply provides a simple Wishbone register interface.
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I could add more logic and create a proper bus master that handles the main state machine
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by itself, but we don't need performance when running I2C so the time spent on that in
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gateware is not worth it.
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Parameters
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----------
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:param system_freq:
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System clock frequency, i.e. frequency present on Wishbone bus.
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:param bus_freq:
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Requested I2C frequency. TODO describe how we create this frequency
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:param clk_stretch:
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Passed through to amlib device, whether or not to monitor for slaves clock stretching.
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Attributes
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----------
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:attr bus:
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CSR bus to access peripheral registers on.
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"""
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def __init__(self, system_freq, bus_freq, pads, clk_stretch: bool = True):
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# Control register, writes to this are strobed into the command interface presented by the
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# amlib implementation
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#
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# Fields:
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# [0]: start - Generate a start or repeated start condition on the bus. Ignored if busy is high
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# [1]: stop - Generate a stop condition on the bus. Ignored if busy is high
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# [2]: write - write a byte out on the bus
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# [3]: read - read a byte from the bus
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# [4]: read_ack - ACK value that gets written out during a read operation
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# [5]: read_ack_en - Hacky solution to determine if we want to save read_ack
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self.CR = Element(6, Element.Access.W, name="CR")
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# Status register
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#
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# Fields:
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# [0]: busy - bus is busy operating
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# [1]: ack - an ACK has been received from a bus slave
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# [2]: read_ack - a convenience read field to see value of CR->read_ack
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self.SR = Element(3, Element.Access.R, name="SR")
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# Data write register
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#
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# Latches in data to be written when write signal is applied.
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self.DWR = Element(8, Element.Access.W, name="DWR")
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# Data read register
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#
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# Only presents valid data after 'read' has started, and once 'busy' is no longer asserted.
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self.DRR = Element(8, Element.Access.R, name="DRR")
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# Set up CSR bus
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addr_width = ceil(log2(64)) # Support up to 64 registers just because
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data_width = 32 # 32 bit bus
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self._csr_mux = Multiplexer(addr_width=addr_width, data_width=data_width)
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# TODO export the addresses of these somehow
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self._csr_mux.add(self.CR)
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self._csr_mux.add(self.SR)
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self._csr_mux.add(self.DWR)
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self._csr_mux.add(self.DRR)
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self.bus = self._csr_mux.bus
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# Set up I2C initiator submodule
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period_cyc = floor(system_freq / bus_freq)
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self._initiator = I2CInitiator(pads, period_cyc, clk_stretch)
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def elaborate(self, _platform):
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m = Module()
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m.submodules.initiator = self._initiator
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m.submodules.csr_mux = self._csr_mux
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# Strobe control signals in
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with m.If(self.CR.w_stb):
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m.d.sync += [
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self._initiator.start.eq(self.CR.w_data[0]),
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self._initiator.stop.eq(self.CR.w_data[1]),
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self._initiator.write.eq(self.CR.w_data[2]),
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self._initiator.read.eq(self.CR.w_data[3]),
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]
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# We don't *always* want to change read_ack
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with m.If(self.CR.w_data[5]):
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m.d.sync += self._initiator.ack_i.eq(self.CR.w_data[4])
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with m.Else():
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m.d.sync += [
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self._initiator.start.eq(0),
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self._initiator.stop.eq(0),
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self._initiator.write.eq(0),
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self._initiator.read.eq(0),
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# We don't strobe ack_i, this is a persistant setting
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]
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# Status signals may as well just be a continuous assignment
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self.SR.r_data[0].eq(self._initiator.busy)
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self.SR.r_data[1].eq(self._initiator.ack_o)
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self.SR.r_data[2].eq(self._initiator.ack_i)
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# Strobe in this byte to send out
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with m.If(self.DWR.w_stb):
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m.d.sync += self._initiator.data_i.eq(self.DWR.w_data)
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# Read data only becomes valid when not busy (i.e. the read has completed)
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with m.If(~self._initiator.busy):
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m.d.sync += self.DRR.r_data.eq(self._initiator.data_o)
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return m
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from amaranth.lib.io import pin_layout
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i2c_layout = [
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("sda", pin_layout(1, "io")),
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("scl", pin_layout(1, "io")),
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]
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class I2CBusSimulator(Elaboratable):
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def __init__(self):
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self.interfaces = []
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self.sda = Signal()
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self.scl = Signal()
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def elaborate(self, target):
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assert target is None, "This bus simulator should never be used in real hardware!"
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n = len(self.interfaces)
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m = Module()
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m.d.comb += self.sda.eq(1)
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m.d.comb += self.scl.eq(1)
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# TODO maybe output a bus contention signal?
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# First interfaces get priority over interfaces added after
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for i in reversed(range(n)):
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# Emulate bus drivers
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with m.If(self.interfaces[i].sda.oe):
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m.d.comb += self.sda.eq(self.interfaces[i].sda.o)
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with m.If(self.interfaces[i].scl.oe):
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m.d.comb += self.scl.eq(self.interfaces[i].scl.o)
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pass
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# Connect inputs to bus value
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m.d.comb += [
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self.interfaces[i].sda.i.eq(self.sda),
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self.interfaces[i].scl.i.eq(self.scl),
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]
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return m
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def create_interface(self) -> Record:
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new_interface = Record(i2c_layout)
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self.interfaces.append(new_interface)
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return new_interface
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class TestHarness(Elaboratable):
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def __init__(self):
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self.i2c = I2CBusSimulator()
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self.uut = I2C(10_000_000, 100_000, self.i2c.create_interface())
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self.i2c_target = I2CTarget(self.i2c.create_interface())
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def elaborate(self, platform):
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assert platform is None
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m = Module()
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m.submodules.i2c = self.i2c
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m.submodules.uut = self.uut
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m.submodules.i2c_target = self.i2c_target
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m.d.comb += self.i2c_target.address.eq(0xAA >> 1)
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return m
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# TODO switch to unittest or something
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if __name__ == "__main__":
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def write_csr(bus, index, data):
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yield bus.addr.eq(index)
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yield bus.w_stb.eq(1)
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yield bus.w_data.eq(data)
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yield Tick()
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yield bus.w_stb.eq(0)
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yield Tick()
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def read_csr(bus, index):
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yield bus.r_strb.eq(1)
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ret = yield bus.r_data
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yield Tick()
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yield bus.r_stb.eq(0)
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yield Tick()
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harness = TestHarness()
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sim = Simulator(harness)
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def test_proc():
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#send start
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yield from write_csr(harness.uut.bus, 0, 1)
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# TODO shouldn't need to do this, if I did a proper CSR read maybe?
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yield Tick()
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yield Tick()
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# TODO I want something like read_csr, unsure how to implement
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# Wait for
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while True:
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busy = yield harness.uut._initiator.busy
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if not busy:
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break
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else:
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yield Tick()
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# Set data
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yield from write_csr(harness.uut.bus, 2, 0xAA)
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# Write data
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yield from write_csr(harness.uut.bus, 0, 1 << 2)
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did_start = False
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for i in range(1000):
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start_cond = yield harness.i2c_target.start
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yield Tick()
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if start_cond:
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did_start = True
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break
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#assert did_start, "Idnaoidnwaioudnwaoiun"
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print(did_start)
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sim.add_clock(100e-9)
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sim.add_sync_process(test_proc)
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with sim.write_vcd('test.vcd'):
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sim.reset()
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sim.run()
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