150 lines
5.2 KiB
Python
150 lines
5.2 KiB
Python
#!/usr/bin/env python3
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from amaranth import *
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from amaranth.sim import *
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from amaranth_boards import colorlight_i9
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from amaranth_soc.wishbone import *
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from minerva.core import Minerva
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from typing import List
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from argparse import ArgumentParser
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from memory import *
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from led import *
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# To change clock domain of a module:
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# new_thing = DomainRenamer("new_clock")(MyElaboratable())
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# TODO clean this up, generate binary here, maybe even run cargo build
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def load_firmware_for_mem() -> List[int]:
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with open('../firmware/fw.bin', 'rb') as f:
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# Stored as little endian, LSB first??
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data = f.read()
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out = []
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assert(len(data) % 4 == 0)
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for i in range(int(len(data) / 4)):
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out.append(int.from_bytes(data[i*4:i*4+4], byteorder='little'))
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return out
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class Core(Elaboratable):
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def __init__(self, led_signal):
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self.count = Signal(64)
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self.cpu = Minerva(reset_address=0x01000000)
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self.arbiter = Arbiter(addr_width=32, data_width=32)
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self.decoder = Decoder(addr_width=32, data_width=32)
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self.led_signal = led_signal
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def elaborate(self, platform):
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m = Module()
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m.submodules.cpu = self.cpu
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m.submodules.arbiter = self.arbiter
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m.submodules.decoder = self.decoder
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# Connect ibus and dbus together for simplicity for now
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minerva_wb_features = ["cti", "bte", "err"]
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self.ibus = Interface(addr_width=32, data_width=32, features=minerva_wb_features)
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# Note this is a set of statements! without assigning to the comb domain, this will do nothing
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m.d.comb += self.cpu.ibus.connect(self.ibus)
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self.arbiter.add(self.ibus)
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self.dbus = Interface(addr_width=32, data_width=32, features=minerva_wb_features)
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m.d.comb += self.cpu.dbus.connect(self.dbus) # Don't use .eq, use .connect, which will appropriately assign signals
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# using .eq() gave me Multiple Driven errors
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self.arbiter.add(self.dbus)
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# TODO do something with interrupts
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# These are interrupts headed into the CPU
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self.interrupts = Signal(32)
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m.d.comb += [
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# Used for mtime registers, which are memory-mapped (not CSR), so I would have to implement.
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# If I cared.
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self.cpu.timer_interrupt.eq(0),
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# Ostensibly exposed to us so we can interrupt one hart (CPU in this context) from another, we don't need this.
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self.cpu.software_interrupt.eq(0),
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# External interrupt lines, would be for any interrupts I implemented w/ a custom interrupt controller.
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# Most likely I'll map a few lines to some peripherals, won't do anything fancy
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self.cpu.external_interrupt.eq(self.interrupts),
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]
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fw = load_firmware_for_mem()
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# Hook up memory space
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self.rom = ROM(fw)
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m.submodules.rom = self.rom
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# Problem: not sure to handle how we do byte vs word addressing properly
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# So doing this shift is a bit of a hacky way to impl anything
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start, _stop, _step = self.decoder.add(self.rom, addr=(0x01000000 >> 2))
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print(f"ROM added at 0x{start:08x}")
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self.ram = RAM()
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m.submodules.ram = self.ram
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start, _stop, _step = self.decoder.add(self.ram)
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print(f"RAM added at 0x{start:08x}")
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self.led = LEDPeripheral(self.led_signal)
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m.submodules.led = self.led
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start, _stop, _step = self.decoder.add(self.led)
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print(f"LED added at 0x{start:08x}")
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# Connect arbiter to decoder
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m.d.comb += self.arbiter.bus.connect(self.decoder.bus)
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# Counter
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#m.d.sync += self.count.eq(self.count + 1)
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#with m.If(self.count >= 50000000):
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# m.d.sync += self.count.eq(0)
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# m.d.sync += led.eq(~led)
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return m
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class SoC(Elaboratable):
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def __init__(self):
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pass
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def elaborate(self, platform):
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if platform is not None:
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led_signal = platform.request("led")
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else:
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# platform is None in simulation, so provide harnesses for required signals
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led_signal = Signal()
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return Core(led_signal)
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# TODO add structure to add regression tests
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def run_sim():
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dut = SoC()
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sim = Simulator(dut)
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def proc():
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for i in range(10000):
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yield Tick()
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sim.add_clock(1e-6)
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sim.add_sync_process(proc)
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with sim.write_vcd('test.vcd', gtkw_file='test.gtkw'):
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sim.reset()
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sim.run()
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if __name__ == "__main__":
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args = ArgumentParser(description="ARVP Sonar Acquisition FPGA gateware.")
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args.add_argument("--build", action="store_true", help="Build bitstream.")
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args.add_argument("--gen-debug-verilog", action="store_true", help="Save debug verilog.")
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# TODO maybe allow an optional arg to specify an individual test to run?
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args.add_argument("--test", action="store_true", help="Run RTL test suite and report results.")
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args.add_argument("--save-vcd", action="store_true", help="Save VCD waveforms from test(s).")
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args = args.parse_args()
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if args.build:
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colorlight_i9.Colorlight_i9_Platform().build(SoC(), debug_verilog=args.gen_debug_verilog)
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if args.test:
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# TODO pass save_vcd arg through
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run_sim()
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