37 lines
1.0 KiB
Python
37 lines
1.0 KiB
Python
from amaranth import *
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from amaranth_soc.wishbone import *
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from amaranth_soc.memory import *
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from math import ceil, log2
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class TimerPeripheral(Elaboratable, Interface):
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def __init__(self, clock_freq: int, wanted_freq: int):
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Interface.__init__(self, addr_width=1, data_width=32, granularity=8)
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memory_map = MemoryMap(addr_width=3, data_width=8)
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self.memory_map = memory_map
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self.ratio = ceil(clock_freq / wanted_freq)
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def elaborate(self, platform):
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m = Module()
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counter = Signal(ceil(log2(self.ratio)))
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value = Signal(32)
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# Up count
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m.d.sync += counter.eq(counter + 1)
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# Divider value reached, increment
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with m.If(counter >= self.ratio):
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m.d.sync += [
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value.eq(value + 1),
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counter.eq(0),
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]
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m.d.sync += self.ack.eq(0)
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with m.If(self.cyc & self.stb):
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m.d.sync += [
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self.ack.eq(1),
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self.dat_r.eq(value),
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]
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return m |