46 lines
1000 B
Rust
46 lines
1000 B
Rust
//! Quick and dirty LiteX uart drier
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const REG_RXTX: u32 = 0;
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const REG_TXFULL: u32 = 0x4;
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//const REG_RXEMPTY: u32 = 0x8;
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use crate::{write_reg, read_reg};
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use core::fmt::Write;
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pub enum Error {
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TxFull,
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RxEmpty,
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}
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pub struct LiteXUart {
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base_addr: u32,
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}
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impl LiteXUart {
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pub fn new(base_addr: u32) -> Self{ Self {base_addr} }
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pub fn try_put_char(&mut self, c: u8) -> Result<(), Error> {
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unsafe {
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if read_reg::<u32>(self.base_addr + REG_TXFULL) != 0 {
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return Err(Error::TxFull);
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}
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write_reg::<u32>(self.base_addr + REG_RXTX, c as u32);
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Ok(())
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}
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}
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}
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impl Write for LiteXUart {
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fn write_str(&mut self, s: &str) -> core::fmt::Result {
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for b in s.as_bytes() {
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// It's okay to loop on this because we'll always clear the buffer
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while let Err(Error::TxFull) = self.try_put_char(*b) {}
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//self.try_put_char(*b);
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}
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Ok(())
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}
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}
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