36 lines
1.0 KiB
Python
36 lines
1.0 KiB
Python
from amaranth import *
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from amaranth_soc.wishbone import *
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from amaranth_soc.memory import *
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class LEDPeripheral(Elaboratable, Interface):
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def __init__(self, led_signal):
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Interface.__init__(self, addr_width=1, data_width=32)
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memory_map = MemoryMap(addr_width=1, data_width=32)
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#memory_map.add_resource("my_led", name="led_peripheral", size=1)
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self.memory_map = memory_map
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self.led = led_signal
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def elaborate(self, platform):
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m = Module()
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storage = Signal(1)
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# Always update read values (both wishbone and the LED outpu)
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m.d.comb += [
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self.dat_r[0].eq(storage),
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self.led.eq(storage),
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]
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m.d.sync += self.ack.eq(0) # default to no ack
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with m.If(self.cyc & self.stb):
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# single cycle ack when CYC and STB are asserted
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m.d.sync += self.ack.eq(1)
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# Write to our storage register if the value has changed
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with m.If(self.we):
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m.d.sync += storage.eq(self.dat_w[0])
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return m
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