David Lenfesty
883b712a53
- The Record.connect() function returns statements that need to be added to the comb domain. - Addressing of the devices works on word-sized chunks, so everything needs to be adjusted there
290 lines
9.4 KiB
Python
290 lines
9.4 KiB
Python
#!/usr/bin/env python3
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from amaranth import *
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from amaranth.sim import *
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from amaranth_boards import colorlight_i9
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from amaranth_soc.wishbone import Interface, Arbiter, Decoder
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from amaranth_soc.memory import MemoryMap
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from typing import List
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from minerva.core import Minerva
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class Blinky(Elaboratable):
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def __init__(self):
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self.count = Signal(64)
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def elaborate(self, platform):
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led = platform.request("led")
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m = Module()
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# Counter
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m.d.sync += self.count.eq(self.count + 1)
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with m.If(self.count >= 50000000):
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m.d.sync += self.count.eq(0)
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m.d.sync += led.eq(~led)
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return m
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# To change clock domain of a module:
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# new_thing = DomainRenamer("new_clock")(MyElaboratable())
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# We sub-class wishbone.Interface here because it needs to be a bus object to be added as a window to Wishbone stuff
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class ROM(Elaboratable, Interface):
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def __init__(self, data=None):
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#self.size = len(data)
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self.data = Memory(width=32, depth=(4096 >> 2), init=data)
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self.r = self.data.read_port()
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# Need to init Interface
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Interface.__init__(self, addr_width=10, data_width=32)
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# This is effectively a "window", and it has a certain set of resources
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# 12 = log2(4096)
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memory_map = MemoryMap(addr_width=10, data_width=32)
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# TODO need to unify how I deal with size
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# In this case, one resource, which is out memory
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memory_map.add_resource(self.data, name="rom_data", size=(4096 >> 2))
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self.memory_map = memory_map
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# Connects memory port signals to wishbone interface
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def elaborate(self, platform):
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# Stolen from https://vivonomicon.com/2020/04/14/learning-fpga-design-with-nmigen/
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m = Module()
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# Register the read port submodule.
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m.submodules.r = self.r
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# 'ack' signal should rest at 0.
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m.d.sync += self.ack.eq( 0 )
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# Simulated reads only take one cycle, but only acknowledge
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# them after 'cyc' and 'stb' are asserted.
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with m.If( self.cyc ):
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m.d.sync += self.ack.eq( self.stb )
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# Set 'dat_r' bus signal to the value in the
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# requested 'data' array index.
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m.d.comb += [
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self.r.addr.eq( self.adr ),
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self.dat_r.eq( self.r.data )
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]
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# End of simulated memory module.
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return m
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# TODO support read segmentation or whatever it's called, where you read/write certian bytes from memory
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# Otherwise we can't store individual bytes, and this will wreck shit in weird ways.
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class RAM(Elaboratable, Interface):
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def __init__(self):
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#self.size = len(data)
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self.data = Memory(width=32, depth=(4096 >> 2))
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self.r = self.data.read_port()
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self.w = self.data.write_port()
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# Need to init Interface
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Interface.__init__(self, addr_width=10, data_width=32)
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# This is effectively a "window", and it has a certain set of resources
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# 12 = log2(4096)
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memory_map = MemoryMap(addr_width=10, data_width=32)
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# TODO need to unify how I deal with size
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# In this case, one resource, which is out memory
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memory_map.add_resource(self.data, name="ram_data", size=(4096 >> 2))
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self.memory_map = memory_map
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# Connects memory port signals to wishbone interface
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def elaborate(self, platform):
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# Stolen from https://vivonomicon.com/2020/04/14/learning-fpga-design-with-nmigen/
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m = Module()
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# Register the read port submodule.
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m.submodules.r = self.r
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m.submodules.w = self.w
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# 'ack' signal should rest at 0.
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m.d.sync += self.ack.eq(0)
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# Simulated reads only take one cycle, but only acknowledge
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# them after 'cyc' and 'stb' are asserted.
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with m.If( self.cyc & self.stb):
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m.d.sync += self.ack.eq(1)
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# Write to address if we are writing
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with m.If(self.we):
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m.d.sync += self.w.en.eq(1)
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# Set 'dat_r' bus signal to the value in the
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# requested 'data' array index.
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m.d.comb += [
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self.r.addr.eq( self.adr ),
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self.dat_r.eq( self.r.data ),
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self.w.addr.eq(self.adr),
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self.w.data.eq(self.dat_w),
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]
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# End of simulated memory module.
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return m
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class LEDPeripheral(Elaboratable, Interface):
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def __init__(self, led_signal):
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Interface.__init__(self, addr_width=1, data_width=32)
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memory_map = MemoryMap(addr_width=1, data_width=32)
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#memory_map.add_resource("my_led", name="led_peripheral", size=1)
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self.memory_map = memory_map
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self.led = led_signal
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def elaborate(self, platform):
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m = Module()
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storage = Signal(1)
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# Always update read values (both wishbone and the LED outpu)
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m.d.comb += [
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self.dat_r[0].eq(storage),
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self.led.eq(storage),
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]
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m.d.sync += self.ack.eq(0) # default to no ack
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with m.If(self.cyc & self.stb):
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# single cycle ack when CYC and STB are asserted
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m.d.sync += self.ack.eq(1)
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# Write to our storage register if the value has changed
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with m.If(self.we):
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m.d.sync += storage.eq(self.dat_w[0])
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return m
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def load_firmware_for_mem() -> List[int]:
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with open('../firmware/fw.bin', 'rb') as f:
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# Stored as little endian, LSB first??
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data = f.read()
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out = []
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assert(len(data) % 4 == 0)
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for i in range(int(len(data) / 4)):
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out.append(int.from_bytes(data[i*4:i*4+4], byteorder='little'))
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return out
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class Core(Elaboratable):
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def __init__(self, led_signal):
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self.count = Signal(64)
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self.cpu = Minerva(reset_address=0x01000000)
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self.arbiter = Arbiter(addr_width=32, data_width=32)
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self.decoder = Decoder(addr_width=32, data_width=32)
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self.led_signal = led_signal
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def elaborate(self, platform):
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m = Module()
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m.submodules += self.cpu
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m.submodules += self.arbiter
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m.submodules += self.decoder
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# Connect ibus and dbus together for simplicity for now
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minerva_wb_features = ["cti", "bte", "err"]
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self.ibus = Interface(addr_width=32, data_width=32, features=minerva_wb_features)
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# Note this is a set of statements! without assigning to the comb domain, this will do nothing
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m.d.comb += self.cpu.ibus.connect(self.ibus)
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self.arbiter.add(self.ibus)
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self.dbus = Interface(addr_width=32, data_width=32, features=minerva_wb_features)
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m.d.comb += self.cpu.dbus.connect(self.dbus) # Don't use .eq, use .connect, which will appropriately assign signals
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# using .eq() gave me Multiple Driven errors
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self.arbiter.add(self.dbus)
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# TODO do something with interrupts
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# These are interrupts headed into the CPU
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self.interrupts = Signal(32)
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m.d.comb += [
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# Used for mtime registers, which are memory-mapped (not CSR), so I would have to implement.
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# If I cared.
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self.cpu.timer_interrupt.eq(0),
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# Ostensibly exposed to us so we can interrupt one hart (CPU in this context) from another, we don't need this.
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self.cpu.software_interrupt.eq(0),
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# External interrupt lines, would be for any interrupts I implemented w/ a custom interrupt controller.
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# Most likely I'll map a few lines to some peripherals, won't do anything fancy
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self.cpu.external_interrupt.eq(self.interrupts),
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]
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fw = load_firmware_for_mem()
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print(len(fw))
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print(fw)
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# Hook up memory space
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self.rom = ROM(fw)
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m.submodules += self.rom
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# Problem: not sure to handle how we do byte vs word addressing properly
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# So doing this shift is a bit of a hacky way to impl anything
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start, _stop, _step = self.decoder.add(self.rom, addr=(0x01000000 >> 2))
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print(f"ROM added at 0x{start:08x}")
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self.ram = RAM()
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m.submodules += self.ram
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start, _stop, _step = self.decoder.add(self.ram)
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print(f"RAM added at 0x{start:08x}")
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self.led = LEDPeripheral(self.led_signal)
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m.submodules += self.led
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start, _stop, _step = self.decoder.add(self.led)
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print(f"LED added at 0x{start:08x}")
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# Connect arbiter to decoder
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m.d.comb += self.arbiter.bus.connect(self.decoder.bus)
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# Counter
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#m.d.sync += self.count.eq(self.count + 1)
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#with m.If(self.count >= 50000000):
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# m.d.sync += self.count.eq(0)
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# m.d.sync += led.eq(~led)
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return m
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class SoC(Elaboratable):
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def __init__(self):
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pass
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def elaborate(self, platform):
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m = Module()
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led_signal = platform.request("led")
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core = Core(led_signal)
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m.submodules += core
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return m
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class TestDevice(Elaboratable):
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def __init__(self):
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pass
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def elaborate(self, platform):
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m = Module()
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led_signal = Signal()
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core = Core(led_signal)
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m.submodules += core
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return m
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def run_sim():
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dut = TestDevice()
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sim = Simulator(dut)
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def proc():
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for i in range(10000):
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yield Tick()
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sim.add_clock(1e-6)
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sim.add_sync_process(proc)
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with sim.write_vcd('test.vcd', gtkw_file='test.gtkw'):
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sim.reset()
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sim.run()
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if __name__ == "__main__":
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colorlight_i9.Colorlight_i9_Platform().build(SoC(), debug_verilog=True)
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#run_sim() |