David Lenfesty
8d00e15835
Bus widths should now all be correct. (addresses and sizes in amaranth take into account the granularity selection, so granularity acts like two extra bits on the bus address line) Also don't ignore a warning about undriven resets. Turns out that can gate *everything* off in your design.
103 lines
3.7 KiB
Python
103 lines
3.7 KiB
Python
from amaranth import *
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from amaranth_soc.wishbone import *
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from amaranth_soc.memory import *
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# TODO impl select
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# We sub-class wishbone.Interface here because it needs to be a bus object to be added as a window to Wishbone stuff
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class ROM(Elaboratable, Interface):
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def __init__(self, data=None):
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#self.size = len(data)
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self.data = Memory(width=32, depth=(4096 >> 2), init=data)
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self.r = self.data.read_port()
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# Need to init Interface
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Interface.__init__(self, addr_width=10, data_width=32, granularity=8)
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# This is effectively a "window", and it has a certain set of resources
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# 12 = log2(4096)
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memory_map = MemoryMap(addr_width=12, data_width=8)
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# TODO need to unify how I deal with size
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# In this case, one resource, which is out memory
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memory_map.add_resource(self.data, name="rom_data", size=(4096 >> 2))
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self.memory_map = memory_map
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# Connects memory port signals to wishbone interface
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def elaborate(self, platform):
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# Stolen from https://vivonomicon.com/2020/04/14/learning-fpga-design-with-nmigen/
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m = Module()
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# Register the read port submodule.
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m.submodules.r = self.r
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# 'ack' signal should rest at 0.
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m.d.sync += self.ack.eq( 0 )
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# Simulated reads only take one cycle, but only acknowledge
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# them after 'cyc' and 'stb' are asserted.
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with m.If( self.cyc ):
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m.d.sync += self.ack.eq( self.stb )
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# Set 'dat_r' bus signal to the value in the
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# requested 'data' array index.
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m.d.comb += [
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self.r.addr.eq( self.adr ),
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self.dat_r.eq( self.r.data )
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]
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# End of simulated memory module.
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return m
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# TODO support read segmentation or whatever it's called, where you read/write certian bytes from memory
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# Otherwise we can't store individual bytes, and this will wreck shit in weird ways.
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class RAM(Elaboratable, Interface):
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def __init__(self):
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#self.size = len(data)
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self.data = Memory(width=32, depth=(4096 >> 2))
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self.r = self.data.read_port()
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self.w = self.data.write_port()
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# Need to init Interface
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Interface.__init__(self, addr_width=10, data_width=32, granularity=8)
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# This is effectively a "window", and it has a certain set of resources
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# 12 = log2(4096)
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memory_map = MemoryMap(addr_width=12, data_width=8)
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# TODO need to unify how I deal with size
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# In this case, one resource, which is out memory
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memory_map.add_resource(self.data, name="ram_data", size=(4096 >> 2))
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self.memory_map = memory_map
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# Connects memory port signals to wishbone interface
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def elaborate(self, platform):
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# Stolen from https://vivonomicon.com/2020/04/14/learning-fpga-design-with-nmigen/
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m = Module()
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# Register the read port submodule.
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m.submodules.r = self.r
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m.submodules.w = self.w
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# 'ack' signal should rest at 0.
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m.d.sync += self.ack.eq(0)
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# Simulated reads only take one cycle, but only acknowledge
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# them after 'cyc' and 'stb' are asserted.
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with m.If( self.cyc & self.stb):
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m.d.sync += self.ack.eq(1)
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# Write to address if we are writing
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with m.If(self.we):
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m.d.sync += self.w.en.eq(1)
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# Set 'dat_r' bus signal to the value in the
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# requested 'data' array index.
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m.d.comb += [
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self.r.addr.eq( self.adr ),
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self.dat_r.eq( self.r.data ),
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self.w.addr.eq(self.adr),
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self.w.data.eq(self.dat_w),
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]
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# End of simulated memory module.
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return m
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