236 lines
11 KiB
Python
Executable File
236 lines
11 KiB
Python
Executable File
#!/usr/bin/env python3
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#
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# This file is part of LiteX-Boards.
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#
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# Copyright (c) 2021 Kazumoto Kojima <kkojima@rr.iij4u.or.jp>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from litex.build.io import DDROutput
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from platforms import sonar as colorlight_i5
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from litex.build.lattice.trellis import trellis_args, trellis_argdict
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.video import VideoHDMIPHY
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from litex.soc.cores.led import LedChaser
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from litex.soc.interconnect.csr import *
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from litedram.modules import M12L64322A # Compatible with EM638325-6H.
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from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
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from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII
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from sampler import Sampler
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from litex.soc.integration.soc import SoCRegion
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from test import run_test, TestResult, skip_suite
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq, use_internal_osc=False, with_usb_pll=False, with_video_pll=False, sdram_rate="1:1"):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain("sys")
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self.clock_domains.cd_sample_clock = ClockDomain("sample_clock")
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if sdram_rate == "1:2":
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self.clock_domains.cd_sys2x = ClockDomain()
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self.clock_domains.cd_sys2x_ps = ClockDomain()
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else:
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self.clock_domains.cd_sys_ps = ClockDomain("sys_ps")
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# # #
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# Clk / Rst
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if not use_internal_osc:
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clk = platform.request("clk25")
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clk_freq = 25e6
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else:
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clk = Signal()
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div = 5
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self.specials += Instance("OSCG",
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p_DIV = div,
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o_OSC = clk
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)
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clk_freq = 310e6/div
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#rst_n = platform.request("cpu_reset_n")
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# PLL
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self.submodules.pll = pll = ECP5PLL()
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self.comb += pll.reset.eq(self.rst)
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pll.register_clkin(clk, clk_freq)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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if sdram_rate == "1:2":
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pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
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pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=180) # Idealy 90° but needs to be increased.
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else:
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pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=180) # Idealy 90° but needs to be increased.
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# SDRAM clock
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sdram_clk = ClockSignal("sys2x_ps" if sdram_rate == "1:2" else "sys_ps")
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self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk)
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# Sampler clock
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pll.create_clkout(self.cd_sample_clock, int(10e6))
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# BaseSoC ------------------------------------------------------------------------------------------
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# TODO make my own platform for this based on the colorlight one, so I can export I2C and other pins
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=60e6, eth_phy=0, with_led_chaser=True, use_internal_osc=False,
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sdram_rate="1:1", with_video_terminal=False, with_video_framebuffer=False,
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**kwargs):
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# TODO change SRAM size
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kwargs["integrated_sram_size"] = 64 * 1024
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kwargs["integrated_rom_init"] = "../firmware/fw.bin"
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platform = colorlight_i5.Platform(board="i9", revision="7.2", toolchain="trellis")
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# CRG --------------------------------------------------------------------------------------
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with_usb_pll = kwargs.get("uart_name", None) == "usb_acm"
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with_video_pll = with_video_terminal or with_video_framebuffer
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self.submodules.crg = _CRG(platform, sys_clk_freq,
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use_internal_osc = use_internal_osc,
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with_usb_pll = with_usb_pll,
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with_video_pll = with_video_pll,
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sdram_rate = sdram_rate
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)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, int(sys_clk_freq), ident = "LiteX SoC on Sonar FPGA", **kwargs)
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# Leds -------------------------------------------------------------------------------------
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if with_led_chaser:
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ledn = platform.request_all("user_led_n")
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self.submodules.leds = LedChaser(pads=ledn, sys_clk_freq=sys_clk_freq)
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# SPI Flash --------------------------------------------------------------------------------
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from litespi.modules import W25Q64 as SpiFlashModule
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from litespi.opcodes import SpiNorFlashOpCodes as Codes
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self.add_spi_flash(mode="1x", module=SpiFlashModule(Codes.READ_1_1_1))
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# SDR SDRAM --------------------------------------------------------------------------------
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#if not self.integrated_main_ram_size:
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# sdrphy_cls = HalfRateGENSDRPHY if sdram_rate == "1:2" else GENSDRPHY
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# self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"))
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# self.add_sdram("sdram",
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# phy = self.sdrphy,
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# module = M12L64322A(sys_clk_freq, sdram_rate),
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# l2_cache_size = kwargs.get("l2_size", 8192)
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# )
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# Ethernet / Etherbone ---------------------------------------------------------------------
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self.submodules.ethphy = LiteEthPHYRGMII(
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clock_pads = self.platform.request("eth_clocks", eth_phy),
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pads = self.platform.request("eth", eth_phy),
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tx_delay = 0)
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self.add_ethernet(phy=self.ethphy)
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# Video ------------------------------------------------------------------------------------
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if with_video_terminal or with_video_framebuffer:
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self.submodules.videophy = VideoHDMIPHY(platform.request("gpdi"), clock_domain="hdmi")
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if with_video_terminal:
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self.add_video_terminal(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi")
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if with_video_framebuffer:
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self.add_video_framebuffer(phy=self.videophy, timings="800x600@60Hz", clock_domain="hdmi")
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self.submodules.sampler = Sampler(platform.request("adc"), self.crg.cd_sample_clock.clk)
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sampler_region = SoCRegion(origin=None, size=0x1000, cached=False)
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#self.add_wb_slave(0x9000_0000, self.sampler.bus, 0x1000)
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## TODO better way to do this?
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#self.bus.add_slave(name="sampler", slave=self.sampler.bus, region=sampler_region)
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# Build --------------------------------------------------------------------------------------------
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def main():
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from litex.soc.integration.soc import LiteXSoCArgumentParser
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parser = LiteXSoCArgumentParser(description="LiteX SoC on Colorlight I5")
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target_group = parser.add_argument_group(title="Target options")
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target_group.add_argument("--build", action="store_true", help="Build design.")
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target_group.add_argument("--load", action="store_true", help="Load bitstream.")
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target_group.add_argument("--sys-clk-freq", default=60e6, help="System clock frequency.")
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sdopts = target_group.add_mutually_exclusive_group()
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sdopts.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support.")
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sdopts.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support.")
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target_group.add_argument("--eth-phy", default=0, type=int, help="Ethernet PHY (0 or 1).")
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target_group.add_argument("--use-internal-osc", action="store_true", help="Use internal oscillator.")
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target_group.add_argument("--sdram-rate", default="1:1", help="SDRAM Rate (1:1 Full Rate or 1:2 Half Rate).")
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viopts = target_group.add_mutually_exclusive_group()
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viopts.add_argument("--with-video-terminal", action="store_true", help="Enable Video Terminal (HDMI).")
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viopts.add_argument("--with-video-framebuffer", action="store_true", help="Enable Video Framebuffer (HDMI).")
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testopts = parser.add_argument_group(title="Testing Options")
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testopts.add_argument("--test", action="store_true", help="Run tests, won't do anything else")
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builder_args(parser)
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soc_core_args(parser)
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trellis_args(parser)
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args = parser.parse_args()
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# Run tests first
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if args.test:
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from sampler import circular_buffer
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from sampler import controller
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from sampler import peak_detector
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results = []
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results.append(run_test("CircularBuffer", circular_buffer.testbench))
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results.append(run_test("SamplerController", controller.test_bus_access))
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results.append(run_test("SamplerController", controller.test_simple_waveform))
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results.append(run_test("SamplerController", controller.test_simple_waveform_capture_offset))
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results.append(run_test("SamplerController", controller.test_multiple_reads))
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results.append(run_test("PeakDetector", peak_detector.test_simple_waveform))
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results.append(run_test("PeakDetector", peak_detector.test_scrunched_simple_waveform))
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results.append(run_test("PeakDetector", peak_detector.test_decay_simple_waveform))
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results.append(run_test("PeakDetector", peak_detector.test_decay_simple_waveform_too_much))
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results.append(run_test("PeakDetector", peak_detector.test_decay_compensates_bias))
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results.append(run_test("PeakDetector", peak_detector.test_biased_simple_waveform))
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results.append(run_test("PeakDetector", peak_detector.test_noise_spike))
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passed = sum((1 for result in results if result.result == TestResult.PASS))
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failed = sum((1 for result in results if result.result == TestResult.FAIL))
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skipped = sum((1 for result in results if result.result == TestResult.SKIP))
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print(f"{passed}/{passed + failed} passed ({skipped} skipped)")
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# TODO maybe don't do this?
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return
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# Build firmware
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import subprocess as sp
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sp.run(["./build_and_strip.sh"], cwd="../firmware").check_returncode()
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soc = BaseSoC(
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sys_clk_freq = int(float(args.sys_clk_freq)),
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eth_phy = args.eth_phy,
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use_internal_osc = args.use_internal_osc,
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sdram_rate = args.sdram_rate,
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with_video_terminal = args.with_video_terminal,
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with_video_framebuffer = args.with_video_framebuffer,
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**soc_core_argdict(args)
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)
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soc.platform.add_extension(colorlight_i5._sdcard_pmod_io)
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if args.with_spi_sdcard:
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soc.add_spi_sdcard()
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if args.with_sdcard:
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soc.add_sdcard()
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builder = Builder(soc, **builder_argdict(args))
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builder_kargs = trellis_argdict(args)
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if args.build:
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builder.build(**builder_kargs)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
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if __name__ == "__main__":
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main()
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