Updated Sonar System

Design Goals

• 4x 20MSPS channels @ > 8 bits
• Ethernet data channel
• Simplified software stack (or at least fewer layers of components)
• Well-documented

System Architecture

┌─────────────┐
│Main Computer│
└─────▲───────┘
      │
      │
      │
┌─────┴──────┐
│Ethernet PHY│
│      ▲     │           Interface Board (x4)
│      │     │       ┌──────────────────────────────┐
│      │     │       │                              │            ┌─────────────┐
│      │     │◄──────┤ LVDS Serializer◄─────────ADC │◄───────────┤ Hydrophones │
│      │     │       │                              │            └─────────────┘
│      │     │       └──────────────────────────────┘
│    FPGA    │
└─────▲──────┘
      │ Dev Board
      │ or
      │ Custom Board
      │
      │
      │
   ┌──┴───────────────────┐
   │ Peak Detector Board  │
   └──────────────────────┘
               (Temporary)

RTL Architecture

Diagram TODO

The plan is to use LiteX and let it do most of the heavy lifting. Components to generate:

• Softcore (microwatt probably, I'm feeling a bit hipster)
• Main memory bus
• DMA engine
• Gigabit Ethernet MAC

THis way the only actual RTL to write is the peripheral that interacts with the ADCs, which should be very simple. To do early bringup I can start with a blinky peripheral to demonstrate access to the bus, and then I can keep adding functionality.

Software Planning

I should be able to target the microwatt with Rust, hopefully do some embassy work and then that gives me a good dev environment.

Should make sure to have a debug port available as early as possible.

I will make the interface as generic as possible, so it should be easy to swap out, but I will start by targetting zmq so I can change as little of the software stack as possible.

Reference for custom target triple