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amaranth-boards@1d82f2ece1
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gateware: first attempt at amaranth SoC
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2023-01-21 22:43:17 -07:00 |
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docs
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gateware: saving some state again
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2023-02-18 11:56:39 -07:00 |
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jtagtap@851b71bb8b
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add jtagdap submodule for now
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2023-03-05 11:52:16 -07:00 |
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liteeth
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gateware: saving some state again
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2023-02-18 11:56:39 -07:00 |
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.gitignore
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gateware: create vcd_out directory by default
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2023-01-29 20:41:17 -07:00 |
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design_notes.md
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Improve top-level docs
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2023-01-23 22:27:45 -07:00 |
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env.bash
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gateware: made basic SoC, mostly just copying existing colorlight target
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2023-01-06 19:03:46 -07:00 |
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eth.py
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gateware: fix dumb mistakes
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2023-03-05 11:43:59 -07:00 |
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gen_liteeth.sh
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gateware: saving some state again
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2023-02-18 11:56:39 -07:00 |
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gen_pll.sh
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gateware: generate PLL with 'ecppll'
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2023-02-25 12:24:03 -07:00 |
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i2c.py
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gateware: saving some WIP on UART
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2023-02-04 12:04:01 -07:00 |
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led.py
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gateware: fix dumb mistakes
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2023-03-05 11:43:59 -07:00 |
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liteeth_config.yaml
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gateware: import basic instance of LiteEth
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2023-02-07 21:00:38 -07:00 |
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main.py
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gateware: fix dumb mistakes
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2023-03-05 11:43:59 -07:00 |
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memory.py
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gateware: fix dumb mistakes
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2023-03-05 11:43:59 -07:00 |
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minerva_notes.md
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Improve top-level docs
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2023-01-23 22:27:45 -07:00 |
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pll.v
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gateware: generate PLL with 'ecppll'
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2023-02-25 12:24:03 -07:00 |
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test_i2c.py
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gateware: test out UART, had to fix SR flags
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2023-02-04 14:40:05 -07:00 |
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test_uart.py
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gateware: test out UART, had to fix SR flags
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2023-02-04 14:40:05 -07:00 |
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test.gtwk
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gateware: saving some state again
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2023-02-18 11:56:39 -07:00 |
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tests.py
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gateware: test out UART, had to fix SR flags
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2023-02-04 14:40:05 -07:00 |
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uart.py
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gateware: test out UART, had to fix SR flags
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2023-02-04 14:40:05 -07:00 |
