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This commit is contained in:
David Lenfesty 2019-11-28 14:20:55 -07:00
parent a628489b2a
commit a1de5eafb6
6 changed files with 735 additions and 0 deletions
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17
final_project/hw/DAC.sch Normal file
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EESchema Schematic File Version 4
LIBS:final_project-cache
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 1 3
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$EndSCHEMATC

173
final_project/hw/amp.sch Normal file
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EESchema Schematic File Version 4
LIBS:final_project-cache
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 3 3
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
Text HLabel 2350 1500 0 50 Input ~ 0
DAC_out
$Comp
L Amplifier_Operational:TL072 U?
U 1 1 5DDEF8DF
P 4500 2400
F 0 "U?" H 4500 2767 50 0000 C CNN
F 1 "TL072" H 4500 2676 50 0000 C CNN
F 2 "" H 4500 2400 50 0001 C CNN
F 3 "http://www.ti.com/lit/ds/symlink/tl071.pdf" H 4500 2400 50 0001 C CNN
1 4500 2400
1 0 0 -1
$EndComp
$Comp
L Amplifier_Operational:TL072 U?
U 2 1 5DDF08AD
P 6350 2650
F 0 "U?" H 6350 3017 50 0000 C CNN
F 1 "TL072" H 6350 2926 50 0000 C CNN
F 2 "" H 6350 2650 50 0001 C CNN
F 3 "http://www.ti.com/lit/ds/symlink/tl071.pdf" H 6350 2650 50 0001 C CNN
2 6350 2650
1 0 0 -1
$EndComp
Wire Wire Line
2350 1500 3050 1500
Wire Wire Line
3050 1500 3050 2300
Wire Wire Line
4150 2500 4200 2500
Text Label 5600 2400 0 50 ~ 0
DIVIDER_OUT
$Comp
L Device:R_POT RV?
U 1 1 5DDFB96D
P 5100 2550
F 0 "RV?" H 5031 2596 50 0000 R CNN
F 1 "R_POT" H 5031 2505 50 0000 R CNN
F 2 "" H 5100 2550 50 0001 C CNN
F 3 "~" H 5100 2550 50 0001 C CNN
1 5100 2550
1 0 0 -1
$EndComp
Wire Wire Line
4800 2400 5100 2400
Wire Wire Line
5100 2700 5100 2900
Wire Wire Line
5100 2900 5050 2900
$Comp
L power:GND #PWR?
U 1 1 5DDFD958
P 5050 2900
F 0 "#PWR?" H 5050 2650 50 0001 C CNN
F 1 "GND" H 5055 2727 50 0000 C CNN
F 2 "" H 5050 2900 50 0001 C CNN
F 3 "" H 5050 2900 50 0001 C CNN
1 5050 2900
1 0 0 -1
$EndComp
Wire Wire Line
5250 2550 6050 2550
Wire Wire Line
4150 2500 4150 2650
Wire Wire Line
4150 2650 4800 2650
Wire Wire Line
4800 2650 4800 2400
Connection ~ 4800 2400
Wire Wire Line
6050 2750 6050 2950
Wire Wire Line
6050 2950 6650 2950
Wire Wire Line
6650 2950 6650 2650
Wire Wire Line
6650 2650 6850 2650
Connection ~ 6650 2650
$Comp
L Device:R R?
U 1 1 5DE007D1
P 6850 2800
F 0 "R?" H 6920 2846 50 0000 L CNN
F 1 "R" H 6920 2755 50 0000 L CNN
F 2 "" V 6780 2800 50 0001 C CNN
F 3 "~" H 6850 2800 50 0001 C CNN
1 6850 2800
1 0 0 -1
$EndComp
$Comp
L Device:R R?
U 1 1 5DE00F57
P 6850 3100
F 0 "R?" H 6920 3146 50 0000 L CNN
F 1 "R" H 6920 3055 50 0000 L CNN
F 2 "" V 6780 3100 50 0001 C CNN
F 3 "~" H 6850 3100 50 0001 C CNN
1 6850 3100
1 0 0 -1
$EndComp
Wire Wire Line
6850 2950 7250 2950
Connection ~ 6850 2950
Wire Wire Line
6850 3250 6850 3350
$Comp
L power:GND #PWR?
U 1 1 5DE01A1C
P 6850 3350
F 0 "#PWR?" H 6850 3100 50 0001 C CNN
F 1 "GND" H 6855 3177 50 0000 C CNN
F 2 "" H 6850 3350 50 0001 C CNN
F 3 "" H 6850 3350 50 0001 C CNN
1 6850 3350
1 0 0 -1
$EndComp
$Comp
L Device:C C?
U 1 1 5DDF1BEF
P 3200 2300
F 0 "C?" V 2948 2300 50 0000 C CNN
F 1 "C" V 3039 2300 50 0000 C CNN
F 2 "" H 3238 2150 50 0001 C CNN
F 3 "~" H 3200 2300 50 0001 C CNN
1 3200 2300
0 1 1 0
$EndComp
$Comp
L Device:R 200k
U 1 1 5DDF226F
P 3700 2450
F 0 "200k" H 3770 2496 50 0000 L CNN
F 1 "R" H 3770 2405 50 0000 L CNN
F 2 "" V 3630 2450 50 0001 C CNN
F 3 "~" H 3700 2450 50 0001 C CNN
1 3700 2450
1 0 0 -1
$EndComp
Wire Wire Line
3350 2300 3700 2300
Wire Wire Line
3700 2300 4200 2300
Connection ~ 3700 2300
Wire Wire Line
3700 2600 3700 2750
$Comp
L power:GND #PWR?
U 1 1 5DDF33D2
P 3700 2750
F 0 "#PWR?" H 3700 2500 50 0001 C CNN
F 1 "GND" H 3705 2577 50 0000 C CNN
F 2 "" H 3700 2750 50 0001 C CNN
F 3 "" H 3700 2750 50 0001 C CNN
1 3700 2750
1 0 0 -1
$EndComp
$EndSCHEMATC

224
final_project/hw/final_project-cache.lib Normal file
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EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# Amplifier_Operational_TL072
#
DEF Amplifier_Operational_TL072 U 0 5 Y Y 3 L N
F0 "U" 0 200 50 H V L CNN
F1 "Amplifier_Operational_TL072" 0 -200 50 H V L CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
ALIAS LM358 AD8620 LMC6062 LMC6082 TL062 TL072 TL082 NE5532 SA5532 RC4558 RC4560 RC4580 LMV358 TS912 TSV912IDT TSV912IST TLC272 TLC277 MCP602 OPA1678 OPA2134 OPA2340 OPA2376xxD OPA2376xxDGK MC33078 MC33178 LM4562 OP249 OP275 ADA4075-2 MCP6002-xP MCP6002-xSN MCP6002-xMS LM7332 OPA2333xxD OPA2333xxDGK LMC6482 LT1492 LTC6081xMS8 LM6172 MCP6L92 NJM2043 NJM2114 NJM4556A NJM4558 NJM4559 NJM4560 NJM4580 NJM5532 ADA4807-2ARM OPA2691 LT6234 OPA2356xxD OPA2356xxDGK OPA1612AxD MC33172 OPA1602 TLV2372 LT6237 OPA2277
$FPLIST
SOIC*3.9x4.9mm*P1.27mm*
DIP*W7.62mm*
TO*99*
OnSemi*Micro8*
TSSOP*3x3mm*P0.65mm*
TSSOP*4.4x3mm*P0.65mm*
MSOP*3x3mm*P0.65mm*
SSOP*3.9x4.9mm*P0.635mm*
LFCSP*2x2mm*P0.5mm*
*SIP*
SOIC*5.3x6.2mm*P1.27mm*
$ENDFPLIST
DRAW
P 4 1 1 10 -200 200 200 0 -200 -200 -200 200 f
P 4 2 1 10 -200 200 200 0 -200 -200 -200 200 f
X ~ 1 300 0 100 L 50 50 1 1 O
X - 2 -300 -100 100 R 50 50 1 1 I
X + 3 -300 100 100 R 50 50 1 1 I
X + 5 -300 100 100 R 50 50 2 1 I
X - 6 -300 -100 100 R 50 50 2 1 I
X ~ 7 300 0 100 L 50 50 2 1 O
X V- 4 -100 -300 150 U 50 50 3 1 W
X V+ 8 -100 300 150 D 50 50 3 1 W
ENDDRAW
ENDDEF
#
# Device_C
#
DEF Device_C C 0 10 N Y 1 F N
F0 "C" 25 100 50 H V L CNN
F1 "Device_C" 25 -100 50 H V L CNN
F2 "" 38 -150 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
C_*
$ENDFPLIST
DRAW
P 2 0 1 20 -80 -30 80 -30 N
P 2 0 1 20 -80 30 80 30 N
X ~ 1 0 150 110 D 50 50 1 1 P
X ~ 2 0 -150 110 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_Crystal
#
DEF Device_Crystal Y 0 40 N N 1 F N
F0 "Y" 0 150 50 H V C CNN
F1 "Device_Crystal" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Crystal*
$ENDFPLIST
DRAW
S -45 100 45 -100 0 1 12 N
P 2 0 1 0 -100 0 -75 0 N
P 2 0 1 20 -75 -50 -75 50 N
P 2 0 1 20 75 -50 75 50 N
P 2 0 1 0 100 0 75 0 N
X 1 1 -150 0 50 R 50 50 1 1 P
X 2 2 150 0 50 L 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_R
#
DEF Device_R R 0 0 N Y 1 F N
F0 "R" 80 0 50 V V C CNN
F1 "Device_R" 0 0 50 V V C CNN
F2 "" -70 0 50 V I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
R_*
$ENDFPLIST
DRAW
S -40 -100 40 100 0 1 10 N
X ~ 1 0 150 50 D 50 50 1 1 P
X ~ 2 0 -150 50 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# Device_R_POT
#
DEF Device_R_POT RV 0 40 Y N 1 F N
F0 "RV" -175 0 50 V V C CNN
F1 "Device_R_POT" -100 0 50 V V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
$FPLIST
Potentiometer*
$ENDFPLIST
DRAW
S 40 100 -40 -100 0 1 10 N
P 2 0 1 0 100 0 60 0 N
P 4 0 1 0 45 0 90 20 90 -20 45 0 F
X 1 1 0 150 50 D 50 50 1 1 P
X 2 2 150 0 50 L 50 50 1 1 P
X 3 3 0 -150 50 U 50 50 1 1 P
ENDDRAW
ENDDEF
#
# MCU_Microchip_ATmega_ATmega328-PU
#
DEF MCU_Microchip_ATmega_ATmega328-PU U 0 20 Y Y 1 F N
F0 "U" -500 1450 50 H V L BNN
F1 "MCU_Microchip_ATmega_ATmega328-PU" 100 -1450 50 H V L TNN
F2 "Package_DIP:DIP-28_W7.62mm" 0 0 50 H I C CIN
F3 "" 0 0 50 H I C CNN
ALIAS ATmega48P-20PU ATmega48A-PU ATmega48PA-PU ATmega88PV-10PU ATmega88P-20PU ATmega88A-PU ATmega88PA-PU ATmega168PV-10PU ATmega168P-20PU ATmega168A-PU ATmega168PA-PU ATmega328-PU ATmega328P-PU
$FPLIST
DIP*W7.62mm*
$ENDFPLIST
DRAW
S -500 -1400 500 1400 0 1 10 f
X ~RESET~/PC6 1 600 -300 100 L 50 50 1 1 T
X XTAL2/PB7 10 600 500 100 L 50 50 1 1 T
X PD5 11 600 -1000 100 L 50 50 1 1 T
X PD6 12 600 -1100 100 L 50 50 1 1 T
X PD7 13 600 -1200 100 L 50 50 1 1 T
X PB0 14 600 1200 100 L 50 50 1 1 T
X PB1 15 600 1100 100 L 50 50 1 1 T
X PB2 16 600 1000 100 L 50 50 1 1 T
X PB3 17 600 900 100 L 50 50 1 1 T
X PB4 18 600 800 100 L 50 50 1 1 T
X PB5 19 600 700 100 L 50 50 1 1 T
X PD0 2 600 -500 100 L 50 50 1 1 T
X AVCC 20 100 1500 100 D 50 50 1 1 W
X AREF 21 -600 1200 100 R 50 50 1 1 P
X GND 22 0 -1500 100 U 50 50 1 1 P N
X PC0 23 600 300 100 L 50 50 1 1 T
X PC1 24 600 200 100 L 50 50 1 1 T
X PC2 25 600 100 100 L 50 50 1 1 T
X PC3 26 600 0 100 L 50 50 1 1 T
X PC4 27 600 -100 100 L 50 50 1 1 T
X PC5 28 600 -200 100 L 50 50 1 1 T
X PD1 3 600 -600 100 L 50 50 1 1 T
X PD2 4 600 -700 100 L 50 50 1 1 T
X PD3 5 600 -800 100 L 50 50 1 1 T
X PD4 6 600 -900 100 L 50 50 1 1 T
X VCC 7 0 1500 100 D 50 50 1 1 W
X GND 8 0 -1500 100 U 50 50 1 1 W
X XTAL1/PB6 9 600 600 100 L 50 50 1 1 T
ENDDRAW
ENDDEF
#
# MCU_Microchip_ATtiny_ATtiny2313-20MU
#
DEF MCU_Microchip_ATtiny_ATtiny2313-20MU U 0 20 Y Y 1 F N
F0 "U" -500 1050 50 H V L BNN
F1 "MCU_Microchip_ATtiny_ATtiny2313-20MU" 100 -1050 50 H V L TNN
F2 "Package_DFN_QFN:MLF-20-1EP_4x4mm_P0.5mm_EP2.6x2.6mm" 0 0 50 H I C CIN
F3 "" 0 0 50 H I C CNN
ALIAS ATtiny2313-20MU ATtiny2313A-MU ATtiny4313-MU
$FPLIST
MLF*1EP*4x4mm*P0.5mm*
$ENDFPLIST
DRAW
S -500 -1000 500 1000 0 1 10 f
X PD1 1 600 -200 100 L 50 50 1 1 T
X PB0 10 600 800 100 L 50 50 1 1 T
X PB1 11 600 700 100 L 50 50 1 1 T
X PB2 12 600 600 100 L 50 50 1 1 T
X PB3 13 600 500 100 L 50 50 1 1 T
X PB4 14 600 400 100 L 50 50 1 1 T
X PB5 15 600 300 100 L 50 50 1 1 T
X PB6 16 600 200 100 L 50 50 1 1 T
X PB7 17 600 100 100 L 50 50 1 1 T
X VCC 18 0 1100 100 D 50 50 1 1 W
X PA2/~RESET 19 -600 800 100 R 50 50 1 1 T
X PA1/XTAL2 2 -600 400 100 R 50 50 1 1 T
X PD0 20 600 -100 100 L 50 50 1 1 T
X GND 21 0 -1100 100 U 50 50 1 1 P N
X PA0/XTAL1 3 -600 600 100 R 50 50 1 1 T
X PD2 4 600 -300 100 L 50 50 1 1 T
X PD3 5 600 -400 100 L 50 50 1 1 T
X PD4 6 600 -500 100 L 50 50 1 1 T
X PD5 7 600 -600 100 L 50 50 1 1 T
X GND 8 0 -1100 100 U 50 50 1 1 W
X PD6 9 600 -700 100 L 50 50 1 1 T
ENDDRAW
ENDDEF
#
# power_+5V
#
DEF power_+5V #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -150 50 H I C CNN
F1 "power_+5V" 0 140 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X +5V 1 0 0 0 U 50 50 1 1 W N
ENDDRAW
ENDDEF
#
# power_GND
#
DEF power_GND #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -250 50 H I C CNN
F1 "power_GND" 0 -150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
X GND 1 0 0 0 D 50 50 1 1 W N
ENDDRAW
ENDDEF
#
#End Library

1
final_project/hw/final_project.kicad_pcb Normal file
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(kicad_pcb (version 4) (host kicad "dummy file") )

33
final_project/hw/final_project.pro Normal file
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update=22/05/2015 07:44:53
version=1
last_client=kicad
[general]
version=1
RootSch=
BoardNm=
[pcbnew]
version=1
LastNetListRead=
UseCmpFile=1
PadDrill=0.600000000000
PadDrillOvalY=0.600000000000
PadSizeH=1.500000000000
PadSizeV=1.500000000000
PcbTextSizeV=1.500000000000
PcbTextSizeH=1.500000000000
PcbTextThickness=0.300000000000
ModuleTextSizeV=1.000000000000
ModuleTextSizeH=1.000000000000
ModuleTextSizeThickness=0.150000000000
SolderMaskClearance=0.000000000000
SolderMaskMinWidth=0.000000000000
DrawSegmentWidth=0.200000000000
BoardOutlineThickness=0.100000000000
ModuleOutlineThickness=0.150000000000
[cvpcb]
version=1
NetIExt=net
[eeschema]
version=1
LibDir=
[eeschema/libraries]

287
final_project/hw/final_project.sch Normal file
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EESchema Schematic File Version 4
LIBS:final_project-cache
EELAYER 30 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 1 3
Title ""
Date ""
Rev ""
Comp ""
Comment1 ""
Comment2 ""
Comment3 ""
Comment4 ""
$EndDescr
$Comp
L MCU_Microchip_ATmega:ATmega328-PU U?
U 1 1 5DDD9932
P 3450 2950
F 0 "U?" H 2806 2996 50 0000 R CNN
F 1 "ATmega328-PU" H 2806 2905 50 0000 R CNN
F 2 "Package_DIP:DIP-28_W7.62mm" H 3450 2950 50 0001 C CIN
F 3 "http://ww1.microchip.com/downloads/en/DeviceDoc/ATmega328_P%20AVR%20MCU%20with%20picoPower%20Technology%20Data%20Sheet%2040001984A.pdf" H 3450 2950 50 0001 C CNN
1 3450 2950
1 0 0 -1
$EndComp
$Comp
L MCU_Microchip_ATtiny:ATtiny2313-20MU U?
U 1 1 5DDDA525
P 7900 2300
F 0 "U?" H 7900 3581 50 0000 C CNN
F 1 "ATtiny2313-20MU" H 7900 3490 50 0000 C CNN
F 2 "Package_DFN_QFN:MLF-20-1EP_4x4mm_P0.5mm_EP2.6x2.6mm" H 7900 2300 50 0001 C CIN
F 3 "http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-2543-AVR-ATtiny2313_Datasheet.pdf" H 7900 2300 50 0001 C CNN
1 7900 2300
1 0 0 -1
$EndComp
Wire Wire Line
4050 2250 4250 2250
Wire Wire Line
4050 2150 4250 2150
Wire Wire Line
4050 2050 4250 2050
Wire Wire Line
4050 1950 4250 1950
Text Label 4250 2250 0 50 ~ 0
SCK
Text Label 4250 2150 0 50 ~ 0
MOSI
Text Label 4250 2050 0 50 ~ 0
MISO
Text Label 4250 1950 0 50 ~ 0
CS
Wire Wire Line
4050 3450 4250 3450
Wire Wire Line
4050 3550 4250 3550
Text Label 4250 3450 0 50 ~ 0
RXD
Text Label 4250 3550 0 50 ~ 0
TXD
$Comp
L Device:Crystal Y?
U 1 1 5DDDDF12
P 4650 2450
F 0 "Y?" V 4604 2581 50 0000 L CNN
F 1 "16MHz" V 4695 2581 50 0000 L CNN
F 2 "" H 4650 2450 50 0001 C CNN
F 3 "~" H 4650 2450 50 0001 C CNN
1 4650 2450
0 1 1 0
$EndComp
Wire Wire Line
4650 2350 4650 2300
Wire Wire Line
4050 2350 4650 2350
Wire Wire Line
4050 2450 4300 2450
Wire Wire Line
4300 2450 4300 2600
Wire Wire Line
4300 2600 4650 2600
Wire Wire Line
4650 2300 5250 2300
Connection ~ 4650 2300
Wire Wire Line
4650 2600 5150 2600
Connection ~ 4650 2600
$Comp
L Device:C C?
U 1 1 5DDDEABA
P 5150 2750
F 0 "C?" H 5265 2796 50 0000 L CNN
F 1 "18p" H 5265 2705 50 0000 L CNN
F 2 "" H 5188 2600 50 0001 C CNN
F 3 "~" H 5150 2750 50 0001 C CNN
1 5150 2750
1 0 0 -1
$EndComp
$Comp
L Device:C C?
U 1 1 5DDDEEAD
P 5250 2450
F 0 "C?" H 5365 2496 50 0000 L CNN
F 1 "18p" H 5365 2405 50 0000 L CNN
F 2 "" H 5288 2300 50 0001 C CNN
F 3 "~" H 5250 2450 50 0001 C CNN
1 5250 2450
1 0 0 -1
$EndComp
Wire Wire Line
5250 2600 5250 2900
Wire Wire Line
5250 2900 5150 2900
Wire Wire Line
5150 2900 5150 3000
Connection ~ 5150 2900
$Comp
L power:GND #PWR?
U 1 1 5DDDF660
P 5150 3000
F 0 "#PWR?" H 5150 2750 50 0001 C CNN
F 1 "GND" H 5155 2827 50 0000 C CNN
F 2 "" H 5150 3000 50 0001 C CNN
F 3 "" H 5150 3000 50 0001 C CNN
1 5150 3000
1 0 0 -1
$EndComp
Wire Wire Line
8500 2400 8700 2400
Wire Wire Line
8500 2500 8700 2500
Text Label 8700 2400 0 50 ~ 0
TXD
Text Label 8700 2500 0 50 ~ 0
RXD
Wire Wire Line
4050 1750 4500 1750
Wire Wire Line
4050 1850 4500 1850
Wire Wire Line
4050 2650 4150 2650
Wire Wire Line
4050 2750 4150 2750
Wire Wire Line
4050 2850 4200 2850
Wire Wire Line
4050 2950 4150 2950
Wire Wire Line
4050 3050 4150 3050
Wire Wire Line
4050 3150 4150 3150
Wire Wire Line
4050 3650 4600 3650
Wire Wire Line
4050 3750 4600 3750
Wire Wire Line
4050 3850 4600 3850
Wire Wire Line
4050 3950 4600 3950
Wire Wire Line
4050 4050 4600 4050
Wire Wire Line
4050 4150 4600 4150
Text Label 4150 2650 0 50 ~ 0
DAC0
Text Label 4150 2750 0 50 ~ 0
DAC1
Text Label 4200 2850 0 50 ~ 0
DAC2
Text Label 4150 2950 0 50 ~ 0
DAC3
Text Label 4150 3050 0 50 ~ 0
DAC4
Text Label 4150 3150 0 50 ~ 0
DAC5
Text Label 4600 3650 0 50 ~ 0
DAC6
Text Label 4600 3750 0 50 ~ 0
DAC7
Text Label 4600 3850 0 50 ~ 0
DAC8
Text Label 4600 3950 0 50 ~ 0
DAC9
Text Label 4600 4050 0 50 ~ 0
DAC10
Text Label 4600 4150 0 50 ~ 0
DAC11
Text Label 4500 1750 0 50 ~ 0
DAC12
Text Label 4500 1850 0 50 ~ 0
DAC13
Wire Wire Line
3450 1450 3450 1300
Wire Wire Line
3450 4450 3450 4600
Wire Wire Line
7900 1200 7900 900
Wire Wire Line
7900 3400 7900 3550
$Comp
L power:+5V #PWR?
U 1 1 5DDEFED6
P 3450 1300
F 0 "#PWR?" H 3450 1150 50 0001 C CNN
F 1 "+5V" H 3465 1473 50 0000 C CNN
F 2 "" H 3450 1300 50 0001 C CNN
F 3 "" H 3450 1300 50 0001 C CNN
1 3450 1300
1 0 0 -1
$EndComp
$Comp
L power:+5V #PWR?
U 1 1 5DDF0261
P 7900 900
F 0 "#PWR?" H 7900 750 50 0001 C CNN
F 1 "+5V" H 7915 1073 50 0000 C CNN
F 2 "" H 7900 900 50 0001 C CNN
F 3 "" H 7900 900 50 0001 C CNN
1 7900 900
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR?
U 1 1 5DDF0E43
P 3450 4600
F 0 "#PWR?" H 3450 4350 50 0001 C CNN
F 1 "GND" H 3455 4427 50 0000 C CNN
F 2 "" H 3450 4600 50 0001 C CNN
F 3 "" H 3450 4600 50 0001 C CNN
1 3450 4600
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR?
U 1 1 5DDF122E
P 7900 3550
F 0 "#PWR?" H 7900 3300 50 0001 C CNN
F 1 "GND" H 7905 3377 50 0000 C CNN
F 2 "" H 7900 3550 50 0001 C CNN
F 3 "" H 7900 3550 50 0001 C CNN
1 7900 3550
1 0 0 -1
$EndComp
Text Label 8500 1500 0 50 ~ 0
LCD_D4
Text Label 8500 1600 0 50 ~ 0
LCD_D5
Text Label 8500 1800 0 50 ~ 0
LCD_D7
Text Label 8500 1700 0 50 ~ 0
LCD_D6
Text Label 8500 1900 0 50 ~ 0
LCD_RS
Text Label 8500 2000 0 50 ~ 0
LCD_RW
Text Label 8500 2700 0 50 ~ 0
BUT1
Text Label 8500 2800 0 50 ~ 0
BUT2
Text Label 8500 2600 0 50 ~ 0
BUT0
NoConn ~ 7300 1500
NoConn ~ 7300 1900
NoConn ~ 8500 2100
NoConn ~ 8500 2200
NoConn ~ 8500 2900
NoConn ~ 8500 3000
NoConn ~ 7300 1700
NoConn ~ 4050 3250
NoConn ~ 2850 1750
NoConn ~ 3550 1450
$Sheet
S 1800 5200 1550 900
U 5DDEEC27
F0 "DAC" 50
F1 "DAC.sch" 50
$EndSheet
$Sheet
S 5450 5300 1450 900
U 5DDEF065
F0 "amp" 50
F1 "amp.sch" 50
F2 "DAC_out" I L 5450 5400 50
$EndSheet
$EndSCHEMATC