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Created VXO7803-1000 3v3 power regulator

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This commit is contained in:
David Lenfesty 2018-07-11 17:46:44 -06:00
parent 8ee713088b
commit cd3cc4749d
3 changed files with 38 additions and 0 deletions
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3
Custom-Parts/power_reg.dcm Normal file
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EESchema-DOCLIB Version 2.0
#
#End Doc Library

19
Custom-Parts/power_reg.lib Normal file
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EESchema-LIBRARY Version 2.3
#encoding utf-8
#
# VXO7803-1000
#
DEF VXO7803-1000 U 0 40 Y Y 1 F N
F0 "U" 300 -200 39 H V C CNN
F1 "VXO7803-1000" 0 150 39 H V C CNN
F2 "" 0 0 39 H V C CNN
F3 "" 0 0 39 H V C CNN
DRAW
S -350 100 350 -150 0 1 0 N
X +VIN 1 -550 0 197 R 50 50 1 1 I
X GND 2 0 -350 197 U 50 50 1 1 I
X +VOUT 3 550 0 197 L 50 50 1 1 I
ENDDRAW
ENDDEF
#
#End Library

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Custom-Parts/power_reg.pretty/VXO7803-1000.kicad_mod Normal file
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(module VXO7803-1000 (layer F.Cu) (tedit 5B469556)
(fp_text reference REF** (at 0 5.715) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value VXO7803-1000 (at 0 -1.8) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -5.8 -1) (end 0 -1) (layer F.SilkS) (width 0.15))
(fp_line (start -5.8 6.5) (end -5.8 -1) (layer F.SilkS) (width 0.15))
(fp_line (start 5.8 6.5) (end -5.8 6.5) (layer F.SilkS) (width 0.15))
(fp_line (start 5.8 -1) (end 5.8 6.5) (layer F.SilkS) (width 0.15))
(fp_line (start 0 -1) (end 5.8 -1) (layer F.SilkS) (width 0.15))
(pad 1 thru_hole circle (at 2.54 0) (size 1.7 1.7) (drill 1.2) (layers *.Cu *.Mask F.SilkS))
(pad 2 thru_hole circle (at 0 0) (size 1.7 1.7) (drill 1.2) (layers *.Cu *.Mask F.SilkS))
(pad 3 thru_hole circle (at -2.54 0) (size 1.7 1.7) (drill 1.2) (layers *.Cu *.Mask F.SilkS))
)