67 lines
1.4 KiB
Markdown
67 lines
1.4 KiB
Markdown
# General Design Notes #
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## STM32 ##
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Vss is ground.
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### Bypass ###
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VDD (pin 16) Needs:
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- 2x 100nF
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- 1x 4.7 uF
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VDDA (pin 5) Needs:
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- 1x 10nF
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- 1x 1uF
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### Pin Stuff ###
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External interrupts can be assigned to any GPIO pin.
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SWDIO is PA13
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SWCLK is PA14
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Internal clock so OSC_IN and OSC_OUT pins can be NC.
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NRST is active low reset.
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### UART Flash Uploading ###
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If BOOT0 is pulled up I think it boots a bootloader that can reprogram flash through USART. Test this out on my dev board.
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Not going to test this, no real sense in doing this when I have an ST-LINK/V2 anyways.
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Pull low to make it use user flash.
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## 74HC595 ##
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RCLK latches data from the shift register to the output register.
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SRCLK clocks in data from SER (and shifts all data around)
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SRCLR clears the shift register
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OE is output enable.
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QH' is an output pin, it clocks out the value in QH.
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## I2C ##
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STM32F030 I2C Pins:
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- PA9: I2C1_SCL
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- PA10: I2C1_SDA
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How do I determine the I2C address?
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- I can hardcode it (annoying to change, have to have seperate binaries)
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- I can listen on I2C...
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I know what to do. Have a default address to listen to, but you can change it over I2C. It stores this address in EEPROM so it persists across reflashes.
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Easy-peasy.
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## Power connections ##
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Load connections, I think I'll just use 0.1" screw terminal headers.
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For the main AC in I'm not sure though.
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## Power Rails ##
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3v3: maybe these modules: VXO78-1000 ? (found in macrofab slack channel) nvm, too high power
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