48 lines
875 B
Markdown
48 lines
875 B
Markdown
# General Design Notes #
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## STM32 ##
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Vss is ground.
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### Bypass ###
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VDD Needs:
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- 2x 100nF
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- 1x 4.7 uF
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VDDA Needs:
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- 1x 10nF
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- 1x 1uF
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### Pin Stuff ###
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External interrupts can be assigned to any GPIO pin.
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SWDIO is PA13
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SWCLK is PA14
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Internal clock so OSC_IN and OSC_OUT pins can be NC.
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NRST is active low reset.
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### UART Flash Uploading ###
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If BOOT0 is pulled up I think it boots a bootloader that can reprogram flash through USART. Test this out on my dev board.
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Not going to test this, no real sense in doing this when I have an ST-LINK/V2 anyways.
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## 74HC595 ##
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RCLK latches data from the shift register to the output register.
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SRCLK clocks in data from SER (and shifts all data around)
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SRCLR clears the shift register
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OE is output enable.
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QH' is an output pin, it clocks out the value in QH.
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## I2C ##
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STM32F030 I2C Pins:
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- PA9: I2C1_SCL
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- PA10: I2C1_SDA
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