gw: finish testing sampler and fix a couple bugs

This commit is contained in:
David Lenfesty 2023-04-23 20:08:17 -06:00
parent dc762bca8d
commit 0bf6c2336c

View File

@ -62,13 +62,13 @@ class CircularBuffer(Module):
empty.eq(0),
# Advance write pointer
If(wr_ptr < depth,
If(wr_ptr < (depth - 1),
wr_ptr.eq(wr_ptr + 1))
.Else(wr_ptr.eq(0)),
# Advance read pointer if we are full (e.g. overwrite old data)
If(~empty & wr_ptr == rd_ptr,
If(rd_ptr < depth,
If(~empty & (wr_ptr == rd_ptr),
If(rd_ptr < (depth - 1),
rd_ptr.eq(rd_ptr + 1))
.Else(rd_ptr.eq(0))
)
@ -91,7 +91,7 @@ class CircularBuffer(Module):
self.comb += [
If(empty, self.len.eq(0))
.Else(
If(wr_ptr >= rd_ptr,
If(wr_ptr > rd_ptr,
self.len.eq(wr_ptr - rd_ptr))
.Elif(wr_ptr != rd_ptr,
self.len.eq(depth - (rd_ptr - wr_ptr)))
@ -106,7 +106,7 @@ class CircularBuffer(Module):
# Technically there's some glitches that can happen here if we write data while clear
# is asserted, but that shouldn't happen and it's fine if it does tbh.
self.sync += If(self.clear,
wr_ptr.eq(0), rd_ptr.eq(0), empty.eq(0))
wr_ptr.eq(0), rd_ptr.eq(0), empty.eq(1))
class Sampler(Module):
@ -146,16 +146,19 @@ def fifo_testbench():
(yield dut.wr_valid.eq(1))
yield
fifo_len = (yield dut.len)
assert fifo_len == 4, f"len should be 4, is {fifo_len}"
# Stop clocking data in
(yield dut.wr_valid.eq(0))
# Tick again because setting a value waits until the next clock...
yield
fifo_len = (yield dut.len)
assert fifo_len == 4, f"len should be 4, is {fifo_len}"
# Reset
(yield dut.clear.eq(1))
yield
(yield dut.cleart.eq(0))
(yield dut.clear.eq(0))
yield
# Len should be cleared
assert (yield dut.len) == 0
@ -168,16 +171,22 @@ def fifo_testbench():
(yield dut.wr_valid.eq(1))
yield
# One more clock
(yield dut.wr_valid.eq(0))
yield
data_len = (yield dut.len)
assert data_len == 24
assert data_len == 24, f"len should be 24, is {data_len}"
out_data = []
for i in range(24):
(yield dut.rd_addr.eq(i))
yield
out_data.append((yield dut.rd_data))
assert out_data[i] == data[i + 8], f"Data mismatch at index {i}"
assert out_data[i] == data[i + 8], f"Data mismatch at index {i}, should be {data[i+8]}, is {out_data[i]}"
# At this point, seems to be working
# At this point, everything seems to be good, so I'm leaving more exhaustive testing
run_simulation(dut, test_fn())