gateware: fix RAM and ROM issues
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@ -57,6 +57,7 @@ class ROM(Elaboratable, Interface):
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class RAM(Elaboratable, Interface):
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class RAM(Elaboratable, Interface):
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def __init__(self, *, size_bytes=4096):
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def __init__(self, *, size_bytes=4096):
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addr_width = ceil(log2(size_bytes >> 2))
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addr_width = ceil(log2(size_bytes >> 2))
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self.addr_width = addr_width
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self.data = Memory(width=32, depth=size_bytes >> 2)
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self.data = Memory(width=32, depth=size_bytes >> 2)
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self.r = self.data.read_port()
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self.r = self.data.read_port()
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self.w = self.data.write_port()
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self.w = self.data.write_port()
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@ -81,6 +82,19 @@ class RAM(Elaboratable, Interface):
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m.submodules.r = self.r
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m.submodules.r = self.r
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m.submodules.w = self.w
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m.submodules.w = self.w
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# TODO not sure if this is the idiomatic way
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self.r.en = Const(1)
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# Default to not writing data
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m.d.sync += self.w.en.eq(0)
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# Use read data to populate un-written wishbone data for sub-32-bit reads
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for i in range(4):
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with m.If(self.sel.bit_select(i, 1)):
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m.d.sync += self.w.data.word_select(i, 8).eq(self.dat_w.word_select(i, 8))
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with m.Else():
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m.d.sync += self.w.data.word_select(i, 8).eq(self.r.data.word_select(i, 8))
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# 'ack' signal should rest at 0.
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# 'ack' signal should rest at 0.
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m.d.sync += self.ack.eq(0)
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m.d.sync += self.ack.eq(0)
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# Simulated reads only take one cycle, but only acknowledge
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# Simulated reads only take one cycle, but only acknowledge
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@ -98,7 +112,7 @@ class RAM(Elaboratable, Interface):
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self.r.addr.eq( self.adr ),
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self.r.addr.eq( self.adr ),
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self.dat_r.eq( self.r.data ),
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self.dat_r.eq( self.r.data ),
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self.w.addr.eq(self.adr),
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self.w.addr.eq(self.adr),
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self.w.data.eq(self.dat_w),
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#self.w.data.eq(self.dat_w),
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]
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]
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# End of simulated memory module.
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# End of simulated memory module.
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