gateware: remove LiteX attempt
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@ -1,14 +0,0 @@
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from migen import *
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from litex.soc.interconnect.csr import *
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from pathlib import Path
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class LedGpio(AutoCSR, Module):
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def __init__(self, platform, led: Signal):
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#source = Path(__file__).parent / "led_gpio.v"
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#platform.add_source(source)
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self.register = CSRStorage(8)
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self.comb += led.eq(self.register.storage[0])
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@ -1,80 +0,0 @@
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`default_nettype none
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module led_gpio #(
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parameter DATA_WIDTH = 32,
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parameter ADR_WIDTH = 32,
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parameter SEL_WIDTH = 4 // ???
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) (
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// Main signals
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input wire clk,
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input wire rst,
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// verilator lint_off UNUSED
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// ---- LiteX Wishbone interface
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// Address
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input wire [ADR_WIDTH-1:0] adr,
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// Data input (write)
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input wire [DATA_WIDTH-1:0] dat_w,
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// Data output (read)
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output reg [DATA_WIDTH-1:0] dat_r,
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// What parts of data are valid?
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input wire [SEL_WIDTH-1:0] sel,
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// Start cycle
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input wire cyc,
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// Enables wishbone interface
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input wire stb,
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// Bus cycle finished
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output reg ack,
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// Is this cycle a read or write?
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input wire we,
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// Cycle type
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input wire [2:0] cti,
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// Burst type
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input wire [1:0] bte,
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// Asserted if cycle completes with error
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output wire err,
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// verilator lint_on UNUSED
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// Output
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output wire led
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);
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// Tracks if we have started a new wishbone cycle. This or similar is needed so we don't
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// think we're handling multiple wishbone cycles inside one.
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reg cycle_started;
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reg led_state;
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always @(posedge clk) begin
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// Always reset the cycle started
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cycle_started <= 0;
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if (rst) begin
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led_state <= 0;
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end else begin
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// TODO ADR checking
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ack <= 0;
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err <= 0; // We never have any bus errors
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dat_r <= 0;
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if (!cycle_started && stb && cyc) begin
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cycle_started <= 1; // Start cycle to be reset next clock
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ack <= 1; // We always acknowledge immediately, we only take one clock to process
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if (we) begin
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// Writes to LED, so we need to assign output
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led_state <= dat_w[0];
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end else begin
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// We want reads to get LED status
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dat_r <= 3;
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end
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end
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end
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end
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always @(*) begin
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led = !led_state;
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end
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endmodule
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`default_nettype wire
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399
gateware/main.py
Executable file → Normal file
399
gateware/main.py
Executable file → Normal file
@ -1,166 +1,303 @@
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#!/usr/bin/env python3
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# General imports
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from migen import *
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from amaranth import *
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from amaranth.sim import *
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from amaranth_boards import colorlight_i9
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from amaranth_soc.wishbone import Interface, Arbiter, Decoder
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from amaranth_soc.memory import MemoryMap
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from litex.build.io import DDROutput
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from minerva.core import Minerva
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from litex_boards.platforms import colorlight_i5
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from typing import List
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from argparse import ArgumentParser
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from litex.build.lattice.trellis import trellis_args, trellis_argdict
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class Blinky(Elaboratable):
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def __init__(self):
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self.count = Signal(64)
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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def elaborate(self, platform):
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led = platform.request("led")
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from litex.soc.interconnect.csr import *
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m = Module()
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from litex.soc.interconnect import wishbone
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from litex.soc.integration.soc import SoCRegion
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# Counter
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m.d.sync += self.count.eq(self.count + 1)
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with m.If(self.count >= 50000000):
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m.d.sync += self.count.eq(0)
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m.d.sync += led.eq(~led)
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from litedram.modules import M12L64322A
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from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
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return m
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from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII
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# To change clock domain of a module:
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# new_thing = DomainRenamer("new_clock")(MyElaboratable())
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# My hardware
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import led_gpio
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# We sub-class wishbone.Interface here because it needs to be a bus object to be added as a window to Wishbone stuff
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class ROM(Elaboratable, Interface):
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def __init__(self, data=None):
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#self.size = len(data)
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self.data = Memory(width=32, depth=(4096 >> 2), init=data)
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self.r = self.data.read_port()
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# Module to configure clocks and resets
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq, use_internal_osc=False, with_usb_pll=False, with_video_pll=False, sdram_rate="1:1"):
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self.rst = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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if sdram_rate == "1:2":
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self.clock_domains.cd_sys2x = ClockDomain()
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self.clock_domains.cd_sys2x_ps = ClockDomain()
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else:
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self.clock_domains.cd_sys_ps = ClockDomain()
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# Need to init Interface
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Interface.__init__(self, addr_width=10, data_width=32)
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# # #
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# This is effectively a "window", and it has a certain set of resources
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# 12 = log2(4096)
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memory_map = MemoryMap(addr_width=10, data_width=32)
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# TODO need to unify how I deal with size
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# In this case, one resource, which is out memory
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memory_map.add_resource(self.data, name="rom_data", size=(4096 >> 2))
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# Clk / Rst
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if not use_internal_osc:
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clk = platform.request("clk25")
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clk_freq = 25e6
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else:
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clk = Signal()
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div = 5
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self.specials += Instance("OSCG",
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p_DIV = div,
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o_OSC = clk
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)
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clk_freq = 310e6/div
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self.memory_map = memory_map
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rst_n = platform.request("cpu_reset_n")
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# Connects memory port signals to wishbone interface
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def elaborate(self, platform):
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# Stolen from https://vivonomicon.com/2020/04/14/learning-fpga-design-with-nmigen/
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m = Module()
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# Register the read port submodule.
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m.submodules.r = self.r
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# PLL
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self.submodules.pll = pll = ECP5PLL()
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self.comb += pll.reset.eq(~rst_n | self.rst)
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pll.register_clkin(clk, clk_freq)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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if sdram_rate == "1:2":
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pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq)
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pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=180) # Idealy 90° but needs to be increased.
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else:
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pll.create_clkout(self.cd_sys_ps, sys_clk_freq, phase=180) # Idealy 90° but needs to be increased.
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# 'ack' signal should rest at 0.
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m.d.sync += self.ack.eq( 0 )
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# Simulated reads only take one cycle, but only acknowledge
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# them after 'cyc' and 'stb' are asserted.
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with m.If( self.cyc ):
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m.d.sync += self.ack.eq( self.stb )
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# USB PLL
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if with_usb_pll:
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self.submodules.usb_pll = usb_pll = ECP5PLL()
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self.comb += usb_pll.reset.eq(~rst_n | self.rst)
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usb_pll.register_clkin(clk, clk_freq)
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self.clock_domains.cd_usb_12 = ClockDomain()
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self.clock_domains.cd_usb_48 = ClockDomain()
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usb_pll.create_clkout(self.cd_usb_12, 12e6, margin=0)
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usb_pll.create_clkout(self.cd_usb_48, 48e6, margin=0)
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# Set 'dat_r' bus signal to the value in the
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# requested 'data' array index.
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m.d.comb += [
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self.r.addr.eq( self.adr ),
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self.dat_r.eq( self.r.data )
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]
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# Video PLL
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if with_video_pll:
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self.submodules.video_pll = video_pll = ECP5PLL()
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self.comb += video_pll.reset.eq(~rst_n | self.rst)
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video_pll.register_clkin(clk, clk_freq)
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self.clock_domains.cd_hdmi = ClockDomain()
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self.clock_domains.cd_hdmi5x = ClockDomain()
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video_pll.create_clkout(self.cd_hdmi, 40e6, margin=0)
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video_pll.create_clkout(self.cd_hdmi5x, 200e6, margin=0)
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# End of simulated memory module.
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return m
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# SDRAM clock
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sdram_clk = ClockSignal("sys2x_ps" if sdram_rate == "1:2" else "sys_ps")
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self.specials += DDROutput(1, 0, platform.request("sdram_clock"), sdram_clk)
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# TODO support read segmentation or whatever it's called, where you read/write certian bytes from memory
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# Otherwise we can't store individual bytes, and this will wreck shit in weird ways.
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class RAM(Elaboratable, Interface):
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def __init__(self):
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#self.size = len(data)
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self.data = Memory(width=32, depth=(4096 >> 2))
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self.r = self.data.read_port()
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self.w = self.data.write_port()
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# Need to init Interface
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Interface.__init__(self, addr_width=10, data_width=32)
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# This is effectively a "window", and it has a certain set of resources
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# 12 = log2(4096)
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memory_map = MemoryMap(addr_width=10, data_width=32)
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# TODO need to unify how I deal with size
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# In this case, one resource, which is out memory
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memory_map.add_resource(self.data, name="ram_data", size=(4096 >> 2))
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self.memory_map = memory_map
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# Connects memory port signals to wishbone interface
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def elaborate(self, platform):
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# Stolen from https://vivonomicon.com/2020/04/14/learning-fpga-design-with-nmigen/
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m = Module()
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# Register the read port submodule.
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m.submodules.r = self.r
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m.submodules.w = self.w
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# 'ack' signal should rest at 0.
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m.d.sync += self.ack.eq(0)
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# Simulated reads only take one cycle, but only acknowledge
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# them after 'cyc' and 'stb' are asserted.
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with m.If( self.cyc & self.stb):
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m.d.sync += self.ack.eq(1)
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# Write to address if we are writing
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with m.If(self.we):
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m.d.sync += self.w.en.eq(1)
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# Set 'dat_r' bus signal to the value in the
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# requested 'data' array index.
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m.d.comb += [
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self.r.addr.eq( self.adr ),
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self.dat_r.eq( self.r.data ),
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self.w.addr.eq(self.adr),
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self.w.data.eq(self.dat_w),
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]
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# End of simulated memory module.
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return m
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class LEDPeripheral(Elaboratable, Interface):
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def __init__(self, led_signal):
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Interface.__init__(self, addr_width=1, data_width=32)
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memory_map = MemoryMap(addr_width=1, data_width=32)
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#memory_map.add_resource("my_led", name="led_peripheral", size=1)
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self.memory_map = memory_map
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self.led = led_signal
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def elaborate(self, platform):
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m = Module()
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storage = Signal(1)
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# Always update read values (both wishbone and the LED outpu)
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m.d.comb += [
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self.dat_r[0].eq(storage),
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self.led.eq(storage),
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]
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m.d.sync += self.ack.eq(0) # default to no ack
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with m.If(self.cyc & self.stb):
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# single cycle ack when CYC and STB are asserted
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m.d.sync += self.ack.eq(1)
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# Write to our storage register if the value has changed
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with m.If(self.we):
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m.d.sync += storage.eq(self.dat_w[0])
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return m
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# SoC definition - this basically instantiates hardware
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class SoC(SoCCore):
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# TODO clean this up, generate binary here, maybe even run cargo build
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def load_firmware_for_mem() -> List[int]:
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with open('../firmware/fw.bin', 'rb') as f:
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# Stored as little endian, LSB first??
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data = f.read()
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out = []
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assert(len(data) % 4 == 0)
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for i in range(int(len(data) / 4)):
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out.append(int.from_bytes(data[i*4:i*4+4], byteorder='little'))
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csr_peripherals = ["led_gpio"]
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#csr_map_update(SoCCore.csr_map, csr_peripherals)
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return out
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# While there are more configurations in what I'm basing this off of, I'm reducing it to
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# one supported config.
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def __init__(self, **kwargs):
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platform = colorlight_i5.Platform(board="i9", revision = "7.2", toolchain="trellis")
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class Core(Elaboratable):
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def __init__(self, led_signal):
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self.count = Signal(64)
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self.cpu = Minerva(reset_address=0x01000000)
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self.arbiter = Arbiter(addr_width=32, data_width=32)
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self.decoder = Decoder(addr_width=32, data_width=32)
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self.led_signal = led_signal
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sys_clk_freq = 50e6
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def elaborate(self, platform):
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m = Module()
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m.submodules.cpu = self.cpu
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m.submodules.arbiter = self.arbiter
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m.submodules.decoder = self.decoder
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self.submodules.crg = _CRG(platform, sys_clk_freq, sdram_rate="1:1")
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# Connect ibus and dbus together for simplicity for now
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minerva_wb_features = ["cti", "bte", "err"]
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self.ibus = Interface(addr_width=32, data_width=32, features=minerva_wb_features)
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# Note this is a set of statements! without assigning to the comb domain, this will do nothing
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m.d.comb += self.cpu.ibus.connect(self.ibus)
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self.arbiter.add(self.ibus)
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# Initialize base SoC core stuff, with given system clock
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SoCCore.__init__(self, platform, int(sys_clk_freq), ident = "Sonar SoC on Colorlight i9", **kwargs)
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self.dbus = Interface(addr_width=32, data_width=32, features=minerva_wb_features)
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m.d.comb += self.cpu.dbus.connect(self.dbus) # Don't use .eq, use .connect, which will appropriately assign signals
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# using .eq() gave me Multiple Driven errors
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self.arbiter.add(self.dbus)
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# Set SPI flash with correct configuration
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from litespi.modules import W25Q64 as SpiFlashModule
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from litespi.opcodes import SpiNorFlashOpCodes as Codes
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# 1x SPI interface (as opposed to QSPI or something), and use the simplest READ timing commands
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self.add_spi_flash(mode="1x", module=SpiFlashModule(Codes.READ_1_1_1))
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# Set up SDRAM
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sdrphy_cls = GENSDRPHY
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self.submodules.sdrphy = sdrphy_cls(platform.request("sdram"))
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self.add_sdram("sdram",
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phy = self.sdrphy,
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module = M12L64322A(sys_clk_freq, "1:1"),
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l2_cache_size = 8192,
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)
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# LED blinky thing
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#wb_interface = wishbone.Interface()
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led = platform.request("user_led_n")
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self.submodules.led_gpio = led_gpio.LedGpio(platform, led)
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#wb_interface.connect_to_pads(led, mode="slave")
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#self.add_memory_region("led_gpio", 0x8F000000, 0x1000, type="dawda")
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#self.add_wb_slave(0x8F000000, wb_interface, 0x1000)
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# vague attempt based on
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#region = SoCRegion(origin=0x8F000000, size=0x1000, cached=False)
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#self.bus.add_slave(name="led_gpio", slave=wb_interface, region=region)
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# TODO ethernet
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# TODO do something with interrupts
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# These are interrupts headed into the CPU
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self.interrupts = Signal(32)
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m.d.comb += [
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# Used for mtime registers, which are memory-mapped (not CSR), so I would have to implement.
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# If I cared.
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self.cpu.timer_interrupt.eq(0),
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# Ostensibly exposed to us so we can interrupt one hart (CPU in this context) from another, we don't need this.
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self.cpu.software_interrupt.eq(0),
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# External interrupt lines, would be for any interrupts I implemented w/ a custom interrupt controller.
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# Most likely I'll map a few lines to some peripherals, won't do anything fancy
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self.cpu.external_interrupt.eq(self.interrupts),
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]
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def main():
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from litex.soc.integration.soc import LiteXSoCArgumentParser
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parser = LiteXSoCArgumentParser(description="LiteX SoC for FPGA sonar")
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target_group = parser.add_argument_group(title="Target options")
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target_group.add_argument("--build", action="store_true", help="Build design")
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target_group.add_argument("--load", action="store_true", help="Load design onto board")
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builder_args(parser)
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soc_core_args(parser)
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trellis_args(parser)
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args = parser.parse_args()
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fw = load_firmware_for_mem()
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soc = SoC(**soc_core_argdict(args))
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# Hook up memory space
|
||||
self.rom = ROM(fw)
|
||||
m.submodules.rom = self.rom
|
||||
# Problem: not sure to handle how we do byte vs word addressing properly
|
||||
# So doing this shift is a bit of a hacky way to impl anything
|
||||
start, _stop, _step = self.decoder.add(self.rom, addr=(0x01000000 >> 2))
|
||||
print(f"ROM added at 0x{start:08x}")
|
||||
|
||||
builder = Builder(soc, **builder_argdict(args))
|
||||
builder_kargs = trellis_argdict(args)
|
||||
if args.build:
|
||||
builder.build(**builder_kargs)
|
||||
self.ram = RAM()
|
||||
m.submodules.ram = self.ram
|
||||
start, _stop, _step = self.decoder.add(self.ram)
|
||||
print(f"RAM added at 0x{start:08x}")
|
||||
|
||||
if args.load:
|
||||
prog = soc.platform.create_programmer()
|
||||
prog.load_bitstream(builder.get_bitstream_filename(mode="sram"))
|
||||
self.led = LEDPeripheral(self.led_signal)
|
||||
m.submodules.led = self.led
|
||||
start, _stop, _step = self.decoder.add(self.led)
|
||||
print(f"LED added at 0x{start:08x}")
|
||||
|
||||
# Connect arbiter to decoder
|
||||
m.d.comb += self.arbiter.bus.connect(self.decoder.bus)
|
||||
|
||||
# Counter
|
||||
#m.d.sync += self.count.eq(self.count + 1)
|
||||
#with m.If(self.count >= 50000000):
|
||||
# m.d.sync += self.count.eq(0)
|
||||
# m.d.sync += led.eq(~led)
|
||||
|
||||
return m
|
||||
|
||||
class SoC(Elaboratable):
|
||||
def __init__(self):
|
||||
pass
|
||||
|
||||
def elaborate(self, platform):
|
||||
m = Module()
|
||||
|
||||
led_signal = platform.request("led")
|
||||
core = Core(led_signal)
|
||||
m.submodules.core = core
|
||||
|
||||
return m
|
||||
|
||||
|
||||
# TODO add more harnessing
|
||||
class TestDevice(Elaboratable):
|
||||
def __init__(self):
|
||||
pass
|
||||
|
||||
|
||||
def elaborate(self, platform):
|
||||
m = Module()
|
||||
led_signal = Signal()
|
||||
core = Core(led_signal)
|
||||
m.submodules.core = core
|
||||
|
||||
return m
|
||||
|
||||
# TODO add structure to add regression tests
|
||||
def run_sim():
|
||||
dut = TestDevice()
|
||||
sim = Simulator(dut)
|
||||
|
||||
def proc():
|
||||
for i in range(10000):
|
||||
yield Tick()
|
||||
|
||||
sim.add_clock(1e-6)
|
||||
sim.add_sync_process(proc)
|
||||
with sim.write_vcd('test.vcd', gtkw_file='test.gtkw'):
|
||||
sim.reset()
|
||||
sim.run()
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
||||
args = ArgumentParser(description="ARVP Sonar Acquisition FPGA gateware.")
|
||||
args.add_argument("--build", action="store_true", help="Build bitstream.")
|
||||
args.add_argument("--gen-debug-verilog", action="store_true", help="Save debug verilog.")
|
||||
# TODO maybe allow an optional arg to specify an individual test to run?
|
||||
args.add_argument("--test", action="store_true", help="Run RTL test suite and report results.")
|
||||
args.add_argument("--save-vcd", action="store_true", help="Save VCD waveforms from test(s).")
|
||||
args = args.parse_args()
|
||||
|
||||
if args.build:
|
||||
colorlight_i9.Colorlight_i9_Platform().build(SoC(), debug_verilog=args.gen_debug_verilog)
|
||||
|
||||
if args.test:
|
||||
# TODO pass save_vcd arg through
|
||||
run_sim()
|
||||
|
||||
303
gateware/soc.py
303
gateware/soc.py
@ -1,303 +0,0 @@
|
||||
#!/usr/bin/env python3
|
||||
|
||||
from amaranth import *
|
||||
from amaranth.sim import *
|
||||
from amaranth_boards import colorlight_i9
|
||||
from amaranth_soc.wishbone import Interface, Arbiter, Decoder
|
||||
from amaranth_soc.memory import MemoryMap
|
||||
|
||||
from minerva.core import Minerva
|
||||
|
||||
from typing import List
|
||||
from argparse import ArgumentParser
|
||||
|
||||
class Blinky(Elaboratable):
|
||||
def __init__(self):
|
||||
self.count = Signal(64)
|
||||
|
||||
def elaborate(self, platform):
|
||||
led = platform.request("led")
|
||||
|
||||
m = Module()
|
||||
|
||||
# Counter
|
||||
m.d.sync += self.count.eq(self.count + 1)
|
||||
with m.If(self.count >= 50000000):
|
||||
m.d.sync += self.count.eq(0)
|
||||
m.d.sync += led.eq(~led)
|
||||
|
||||
return m
|
||||
|
||||
# To change clock domain of a module:
|
||||
# new_thing = DomainRenamer("new_clock")(MyElaboratable())
|
||||
|
||||
# We sub-class wishbone.Interface here because it needs to be a bus object to be added as a window to Wishbone stuff
|
||||
class ROM(Elaboratable, Interface):
|
||||
def __init__(self, data=None):
|
||||
#self.size = len(data)
|
||||
self.data = Memory(width=32, depth=(4096 >> 2), init=data)
|
||||
self.r = self.data.read_port()
|
||||
|
||||
# Need to init Interface
|
||||
Interface.__init__(self, addr_width=10, data_width=32)
|
||||
|
||||
# This is effectively a "window", and it has a certain set of resources
|
||||
# 12 = log2(4096)
|
||||
memory_map = MemoryMap(addr_width=10, data_width=32)
|
||||
# TODO need to unify how I deal with size
|
||||
# In this case, one resource, which is out memory
|
||||
memory_map.add_resource(self.data, name="rom_data", size=(4096 >> 2))
|
||||
|
||||
self.memory_map = memory_map
|
||||
|
||||
# Connects memory port signals to wishbone interface
|
||||
def elaborate(self, platform):
|
||||
# Stolen from https://vivonomicon.com/2020/04/14/learning-fpga-design-with-nmigen/
|
||||
m = Module()
|
||||
# Register the read port submodule.
|
||||
m.submodules.r = self.r
|
||||
|
||||
# 'ack' signal should rest at 0.
|
||||
m.d.sync += self.ack.eq( 0 )
|
||||
# Simulated reads only take one cycle, but only acknowledge
|
||||
# them after 'cyc' and 'stb' are asserted.
|
||||
with m.If( self.cyc ):
|
||||
m.d.sync += self.ack.eq( self.stb )
|
||||
|
||||
# Set 'dat_r' bus signal to the value in the
|
||||
# requested 'data' array index.
|
||||
m.d.comb += [
|
||||
self.r.addr.eq( self.adr ),
|
||||
self.dat_r.eq( self.r.data )
|
||||
]
|
||||
|
||||
# End of simulated memory module.
|
||||
return m
|
||||
|
||||
# TODO support read segmentation or whatever it's called, where you read/write certian bytes from memory
|
||||
# Otherwise we can't store individual bytes, and this will wreck shit in weird ways.
|
||||
class RAM(Elaboratable, Interface):
|
||||
def __init__(self):
|
||||
#self.size = len(data)
|
||||
self.data = Memory(width=32, depth=(4096 >> 2))
|
||||
self.r = self.data.read_port()
|
||||
self.w = self.data.write_port()
|
||||
|
||||
# Need to init Interface
|
||||
Interface.__init__(self, addr_width=10, data_width=32)
|
||||
|
||||
# This is effectively a "window", and it has a certain set of resources
|
||||
# 12 = log2(4096)
|
||||
memory_map = MemoryMap(addr_width=10, data_width=32)
|
||||
# TODO need to unify how I deal with size
|
||||
# In this case, one resource, which is out memory
|
||||
memory_map.add_resource(self.data, name="ram_data", size=(4096 >> 2))
|
||||
|
||||
self.memory_map = memory_map
|
||||
|
||||
# Connects memory port signals to wishbone interface
|
||||
def elaborate(self, platform):
|
||||
# Stolen from https://vivonomicon.com/2020/04/14/learning-fpga-design-with-nmigen/
|
||||
m = Module()
|
||||
# Register the read port submodule.
|
||||
m.submodules.r = self.r
|
||||
m.submodules.w = self.w
|
||||
|
||||
# 'ack' signal should rest at 0.
|
||||
m.d.sync += self.ack.eq(0)
|
||||
# Simulated reads only take one cycle, but only acknowledge
|
||||
# them after 'cyc' and 'stb' are asserted.
|
||||
with m.If( self.cyc & self.stb):
|
||||
m.d.sync += self.ack.eq(1)
|
||||
|
||||
# Write to address if we are writing
|
||||
with m.If(self.we):
|
||||
m.d.sync += self.w.en.eq(1)
|
||||
|
||||
# Set 'dat_r' bus signal to the value in the
|
||||
# requested 'data' array index.
|
||||
m.d.comb += [
|
||||
self.r.addr.eq( self.adr ),
|
||||
self.dat_r.eq( self.r.data ),
|
||||
self.w.addr.eq(self.adr),
|
||||
self.w.data.eq(self.dat_w),
|
||||
]
|
||||
|
||||
# End of simulated memory module.
|
||||
return m
|
||||
|
||||
class LEDPeripheral(Elaboratable, Interface):
|
||||
def __init__(self, led_signal):
|
||||
Interface.__init__(self, addr_width=1, data_width=32)
|
||||
memory_map = MemoryMap(addr_width=1, data_width=32)
|
||||
#memory_map.add_resource("my_led", name="led_peripheral", size=1)
|
||||
self.memory_map = memory_map
|
||||
|
||||
self.led = led_signal
|
||||
|
||||
def elaborate(self, platform):
|
||||
m = Module()
|
||||
|
||||
storage = Signal(1)
|
||||
|
||||
# Always update read values (both wishbone and the LED outpu)
|
||||
m.d.comb += [
|
||||
self.dat_r[0].eq(storage),
|
||||
self.led.eq(storage),
|
||||
]
|
||||
|
||||
m.d.sync += self.ack.eq(0) # default to no ack
|
||||
with m.If(self.cyc & self.stb):
|
||||
# single cycle ack when CYC and STB are asserted
|
||||
m.d.sync += self.ack.eq(1)
|
||||
|
||||
# Write to our storage register if the value has changed
|
||||
with m.If(self.we):
|
||||
m.d.sync += storage.eq(self.dat_w[0])
|
||||
|
||||
return m
|
||||
|
||||
|
||||
# TODO clean this up, generate binary here, maybe even run cargo build
|
||||
def load_firmware_for_mem() -> List[int]:
|
||||
with open('../firmware/fw.bin', 'rb') as f:
|
||||
# Stored as little endian, LSB first??
|
||||
data = f.read()
|
||||
out = []
|
||||
assert(len(data) % 4 == 0)
|
||||
for i in range(int(len(data) / 4)):
|
||||
out.append(int.from_bytes(data[i*4:i*4+4], byteorder='little'))
|
||||
|
||||
return out
|
||||
|
||||
class Core(Elaboratable):
|
||||
def __init__(self, led_signal):
|
||||
self.count = Signal(64)
|
||||
self.cpu = Minerva(reset_address=0x01000000)
|
||||
self.arbiter = Arbiter(addr_width=32, data_width=32)
|
||||
self.decoder = Decoder(addr_width=32, data_width=32)
|
||||
self.led_signal = led_signal
|
||||
|
||||
def elaborate(self, platform):
|
||||
m = Module()
|
||||
m.submodules.cpu = self.cpu
|
||||
m.submodules.arbiter = self.arbiter
|
||||
m.submodules.decoder = self.decoder
|
||||
|
||||
# Connect ibus and dbus together for simplicity for now
|
||||
minerva_wb_features = ["cti", "bte", "err"]
|
||||
self.ibus = Interface(addr_width=32, data_width=32, features=minerva_wb_features)
|
||||
# Note this is a set of statements! without assigning to the comb domain, this will do nothing
|
||||
m.d.comb += self.cpu.ibus.connect(self.ibus)
|
||||
self.arbiter.add(self.ibus)
|
||||
|
||||
self.dbus = Interface(addr_width=32, data_width=32, features=minerva_wb_features)
|
||||
m.d.comb += self.cpu.dbus.connect(self.dbus) # Don't use .eq, use .connect, which will appropriately assign signals
|
||||
# using .eq() gave me Multiple Driven errors
|
||||
self.arbiter.add(self.dbus)
|
||||
|
||||
# TODO do something with interrupts
|
||||
# These are interrupts headed into the CPU
|
||||
self.interrupts = Signal(32)
|
||||
m.d.comb += [
|
||||
# Used for mtime registers, which are memory-mapped (not CSR), so I would have to implement.
|
||||
# If I cared.
|
||||
self.cpu.timer_interrupt.eq(0),
|
||||
# Ostensibly exposed to us so we can interrupt one hart (CPU in this context) from another, we don't need this.
|
||||
self.cpu.software_interrupt.eq(0),
|
||||
# External interrupt lines, would be for any interrupts I implemented w/ a custom interrupt controller.
|
||||
# Most likely I'll map a few lines to some peripherals, won't do anything fancy
|
||||
self.cpu.external_interrupt.eq(self.interrupts),
|
||||
]
|
||||
|
||||
|
||||
fw = load_firmware_for_mem()
|
||||
|
||||
# Hook up memory space
|
||||
self.rom = ROM(fw)
|
||||
m.submodules.rom = self.rom
|
||||
# Problem: not sure to handle how we do byte vs word addressing properly
|
||||
# So doing this shift is a bit of a hacky way to impl anything
|
||||
start, _stop, _step = self.decoder.add(self.rom, addr=(0x01000000 >> 2))
|
||||
print(f"ROM added at 0x{start:08x}")
|
||||
|
||||
self.ram = RAM()
|
||||
m.submodules.ram = self.ram
|
||||
start, _stop, _step = self.decoder.add(self.ram)
|
||||
print(f"RAM added at 0x{start:08x}")
|
||||
|
||||
self.led = LEDPeripheral(self.led_signal)
|
||||
m.submodules.led = self.led
|
||||
start, _stop, _step = self.decoder.add(self.led)
|
||||
print(f"LED added at 0x{start:08x}")
|
||||
|
||||
# Connect arbiter to decoder
|
||||
m.d.comb += self.arbiter.bus.connect(self.decoder.bus)
|
||||
|
||||
# Counter
|
||||
#m.d.sync += self.count.eq(self.count + 1)
|
||||
#with m.If(self.count >= 50000000):
|
||||
# m.d.sync += self.count.eq(0)
|
||||
# m.d.sync += led.eq(~led)
|
||||
|
||||
return m
|
||||
|
||||
class SoC(Elaboratable):
|
||||
def __init__(self):
|
||||
pass
|
||||
|
||||
def elaborate(self, platform):
|
||||
m = Module()
|
||||
|
||||
led_signal = platform.request("led")
|
||||
core = Core(led_signal)
|
||||
m.submodules.core = core
|
||||
|
||||
return m
|
||||
|
||||
|
||||
# TODO add more harnessing
|
||||
class TestDevice(Elaboratable):
|
||||
def __init__(self):
|
||||
pass
|
||||
|
||||
|
||||
def elaborate(self, platform):
|
||||
m = Module()
|
||||
led_signal = Signal()
|
||||
core = Core(led_signal)
|
||||
m.submodules.core = core
|
||||
|
||||
return m
|
||||
|
||||
# TODO add structure to add regression tests
|
||||
def run_sim():
|
||||
dut = TestDevice()
|
||||
sim = Simulator(dut)
|
||||
|
||||
def proc():
|
||||
for i in range(10000):
|
||||
yield Tick()
|
||||
|
||||
sim.add_clock(1e-6)
|
||||
sim.add_sync_process(proc)
|
||||
with sim.write_vcd('test.vcd', gtkw_file='test.gtkw'):
|
||||
sim.reset()
|
||||
sim.run()
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
args = ArgumentParser(description="ARVP Sonar Acquisition FPGA gateware.")
|
||||
args.add_argument("--build", action="store_true", help="Build bitstream.")
|
||||
args.add_argument("--gen-debug-verilog", action="store_true", help="Save debug verilog.")
|
||||
# TODO maybe allow an optional arg to specify an individual test to run?
|
||||
args.add_argument("--test", action="store_true", help="Run RTL test suite and report results.")
|
||||
args.add_argument("--save-vcd", action="store_true", help="Save VCD waveforms from test(s).")
|
||||
args = args.parse_args()
|
||||
|
||||
if args.build:
|
||||
colorlight_i9.Colorlight_i9_Platform().build(SoC(), debug_verilog=args.gen_debug_verilog)
|
||||
|
||||
if args.test:
|
||||
# TODO pass save_vcd arg through
|
||||
run_sim()
|
||||
Loading…
Reference in New Issue
Block a user