tracking a couple files I missed
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38
firmware/src/logging.rs
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38
firmware/src/logging.rs
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use core::{fmt::Write, any::Any};
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use defmt;
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use crate::uart::AmlibUart;
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use core::arch::asm;
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#[defmt::global_logger]
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struct DefmtLogger;
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unsafe impl defmt::Logger for DefmtLogger {
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fn acquire() {
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// Sync methods left empty because we don't use any interrupts
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}
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unsafe fn flush() {
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// Sync methods left empty because we don't use any interrupts
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}
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unsafe fn release() {
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// Sync methods left empty because we don't use any interrupts
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}
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unsafe fn write(bytes: &[u8]) {
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static mut UART: Option<AmlibUart> = None;
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if UART.is_none() {
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UART = Some(AmlibUart::new(0x0200_0040));
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}
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let mut dev = UART.unwrap();
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//writeln!(dev, "a").unwrap();
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//writeln!(dev, "length: {}", bytes.len());
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for byte in bytes {
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while let Err(_) = dev.try_put_char(*byte) {}
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}
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}
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}
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37
gateware/timer.py
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37
gateware/timer.py
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from amaranth import *
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from amaranth_soc.wishbone import *
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from amaranth_soc.memory import *
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from math import ceil, log2
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class TimerPeripheral(Elaboratable, Interface):
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def __init__(self, clock_freq: int, wanted_freq: int):
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Interface.__init__(self, addr_width=1, data_width=32, granularity=8)
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memory_map = MemoryMap(addr_width=3, data_width=8)
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self.memory_map = memory_map
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self.ratio = ceil(clock_freq / wanted_freq)
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def elaborate(self, platform):
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m = Module()
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counter = Signal(ceil(log2(self.ratio)))
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value = Signal(32)
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# Up count
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m.d.sync += counter.eq(counter + 1)
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# Divider value reached, increment
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with m.If(counter >= self.ratio):
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m.d.sync += [
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value.eq(value + 1),
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counter.eq(0),
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]
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m.d.sync += self.ack.eq(0)
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with m.If(self.cyc & self.stb):
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m.d.sync += [
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self.ack.eq(1),
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self.dat_r.eq(value),
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]
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return m
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