tracking a couple files I missed

This commit is contained in:
David Lenfesty 2023-04-16 11:06:02 -06:00
parent 9b49f1184e
commit 29ec5a8a43
2 changed files with 75 additions and 0 deletions

38
firmware/src/logging.rs Normal file
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use core::{fmt::Write, any::Any};
use defmt;
use crate::uart::AmlibUart;
use core::arch::asm;
#[defmt::global_logger]
struct DefmtLogger;
unsafe impl defmt::Logger for DefmtLogger {
fn acquire() {
// Sync methods left empty because we don't use any interrupts
}
unsafe fn flush() {
// Sync methods left empty because we don't use any interrupts
}
unsafe fn release() {
// Sync methods left empty because we don't use any interrupts
}
unsafe fn write(bytes: &[u8]) {
static mut UART: Option<AmlibUart> = None;
if UART.is_none() {
UART = Some(AmlibUart::new(0x0200_0040));
}
let mut dev = UART.unwrap();
//writeln!(dev, "a").unwrap();
//writeln!(dev, "length: {}", bytes.len());
for byte in bytes {
while let Err(_) = dev.try_put_char(*byte) {}
}
}
}

37
gateware/timer.py Normal file
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from amaranth import *
from amaranth_soc.wishbone import *
from amaranth_soc.memory import *
from math import ceil, log2
class TimerPeripheral(Elaboratable, Interface):
def __init__(self, clock_freq: int, wanted_freq: int):
Interface.__init__(self, addr_width=1, data_width=32, granularity=8)
memory_map = MemoryMap(addr_width=3, data_width=8)
self.memory_map = memory_map
self.ratio = ceil(clock_freq / wanted_freq)
def elaborate(self, platform):
m = Module()
counter = Signal(ceil(log2(self.ratio)))
value = Signal(32)
# Up count
m.d.sync += counter.eq(counter + 1)
# Divider value reached, increment
with m.If(counter >= self.ratio):
m.d.sync += [
value.eq(value + 1),
counter.eq(0),
]
m.d.sync += self.ack.eq(0)
with m.If(self.cyc & self.stb):
m.d.sync += [
self.ack.eq(1),
self.dat_r.eq(value),
]
return m