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gateware/i2c: flesh out full R/W transaction in test

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This commit is contained in:
David Lenfesty 2023-01-30 10:09:28 -07:00
parent f0683e684c
commit 71ca5a31be
1 changed files with 33 additions and 2 deletions
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35
gateware/test_i2c.py
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@ -28,6 +28,8 @@ class TestHarness(Elaboratable):
m.submodules.i2c_target = self.i2c_target
m.d.comb += self.i2c_target.address.eq(0xAA >> 1)
# Always ACK
m.d.comb += self.i2c_target.ack_o.eq(1)
with m.If(self.i2c_target.start):
m.d.sync += self.start_latch.eq(self.i2c_target.start)
@ -76,8 +78,8 @@ class TestCSROperation(BaseTestClass):
@provide_testcase_name
def test_operation(self, test_name):
def test():
#send start
yield from self._write_csr(self.harness.uut.bus, 0, 1)
#send start (and set ACK)
yield from self._write_csr(self.harness.uut.bus, 0, 1 + (1 << 4) + (1 << 5))
yield from self._wait_for_signal(self.harness.uut._initiator.busy, require_edge=True)
@ -92,6 +94,35 @@ class TestCSROperation(BaseTestClass):
did_start = yield self.harness.start_latch
self.assertTrue(did_start)
did_ack = yield self.harness.uut._initiator.ack_o
self.assertTrue(did_ack)
# Write data again
yield from self._write_csr(self.harness.uut.bus, 0, 1 << 2)
yield from self._wait_for_signal(self.harness.uut._initiator.busy)
# Repeated start
yield from self._write_csr(self.harness.uut.bus, 0, 1)
yield from self._wait_for_signal(self.harness.uut._initiator.busy)
# Write read thing
yield from self._write_csr(self.harness.uut.bus, 2, 0xAB) # Set R/W bit for a read
yield from self._write_csr(self.harness.uut.bus, 0, 1 << 2)
yield from self._wait_for_signal(self.harness.uut._initiator.busy)
# Read
yield from self._write_csr(self.harness.uut.bus, 0, 1 << 3)
yield from self._wait_for_signal(self.harness.uut._initiator.busy)
# Stop
yield from self._write_csr(self.harness.uut.bus, 0, 1 << 1)
yield from self._wait_for_signal(self.harness.uut._initiator.busy)
# I just feel weird seeing it cut out *right* at the end
for i in range(500):
yield Tick()
self._run_test(test, test_name)