start playing around with sampler (not working at all, wb issues I think)
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1b08dfa2a1
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@ -2,7 +2,8 @@
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DEFMT_LOG=debug cargo build --release
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if [ $? -ne 0 ]
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then
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exit $?
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# Can't use $? because the check itself also updates the return code
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exit 1
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fi
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# Account for different toolchains
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@ -32,6 +32,7 @@ mod logging;
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mod mcp4726;
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mod proto;
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mod uart;
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mod sampler;
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const MAC: [u8; 6] = [0xA0, 0xBB, 0xCC, 0xDD, 0xEE, 0xF0];
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@ -93,6 +94,18 @@ fn main() -> ! {
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sock.set_timeout(Some(Duration::from_secs(10)))
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}
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let mut data_tx_storage = [0u8; 256];
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let mut data_rx_storage = [0u8; 24];
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let mut data_tx_buf = SocketBuffer::new(&mut data_tx_storage[..]);
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let mut data_rx_buf = SocketBuffer::new(&mut data_rx_storage[..]);
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let mut data_socket = socket_set.add(TcpSocket::new(data_tx_buf, data_rx_buf));
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{
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let mut sock = socket_set.get_mut::<TcpSocket>(data_socket);
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// TODO these values are obscene, should fix the underlying bug
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sock.set_keep_alive(Some(Duration::from_secs(2)));
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sock.set_timeout(Some(Duration::from_secs(10)))
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}
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let mut last_blink: u32 = 0;
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let mut toggle = false;
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//defmt::info!("Done setup");
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@ -110,23 +123,41 @@ fn main() -> ! {
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loop {
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let now = millis();
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iface.poll(Instant::from_millis(now), &mut device, &mut socket_set);
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// TODO first connection to a socket takes a while to establish, and can time out, why?
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cmd.run(socket_set.get_mut(command_socket));
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// TODO the need for the second check screams something is unsound somewhere
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if now - last_blink > 1000 && now > last_blink {
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last_blink = now;
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toggle = !toggle;
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write_led(if toggle { 1 } else { 0 });
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let val: u32 = unsafe { read_reg(0x8000_2000) };
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let mut sock = socket_set.get_mut::<TcpSocket>(data_socket);
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if !sock.is_open() {
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sock.listen(3000);
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}
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if toggle {
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sampler::clear_buffers();
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sampler::start_sampling();
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let buf = unsafe {sampler::get_sample_buffer(0) };
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let status = sampler::read_status();
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let raw_reg: u32 = unsafe { read_reg(0x8040_0004) };
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defmt::debug!("Start: len: {}, complete: {}, running: {}, status: {}", buf.len(), status.capture_complete, status.sampling, raw_reg);
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} else {
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sampler::stop_sampling();
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let buf = unsafe {sampler::get_sample_buffer(0) };
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defmt::debug!("Stopped, len: {}", buf.len());
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}
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}
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// TODO I think the timer might actually stop until the event is cleared? this may pose
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// problems, might explain why moving this above the smoltcp stuff "broke" things
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handle_timer_event();
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iface.poll(Instant::from_millis(now), &mut device, &mut socket_set);
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// TODO first connection to a socket takes a while to establish, and can time out, why?
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cmd.run(socket_set.get_mut(command_socket));
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}
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}
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@ -53,6 +53,8 @@ pub enum Settings {
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CenterFreq = 5,
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/// Sampling enabled, 1 to enable, 0 to disable
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SamplingEnabled = 6,
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/// Number of samples acquired after trigger
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TriggerRunLen = 7,
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}
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#[derive(Clone, Copy, Debug)]
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@ -146,7 +146,7 @@ class BaseSoC(SoCCore):
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samplers = [Sampler(platform.request("adc", i)) for i in range(3)]
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self.submodules.sampler_controller = SamplerController(samplers, buffer_len=2048 * 10)
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# TODO better way to do this?
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sampler_region = SoCRegion(origin=None, size=0x4000, cached=False)
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sampler_region = SoCRegion(origin=None, size=0x0040_0000, cached=False)
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self.bus.add_slave(name="sampler", slave=self.sampler_controller.bus, region=sampler_region)
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# Build --------------------------------------------------------------------------------------------
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@ -27,11 +27,16 @@ _io_v7_0 = [ # Colorlight i9 documented by @smunaut
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("user_led_n", 0, Pins("U16"), IOStandard("LVCMOS33")),
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# Serial
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("serial", 0,
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("serial", 2,
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Subsignal("tx", Pins("P16")),
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Subsignal("rx", Pins("L5")),
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IOStandard("LVCMOS33")
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),
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("serial", 3,
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Subsignal("tx", Pins("J18")),
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Subsignal("rx", Pins("J16")),
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IOStandard("LVCMOS33")
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),
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# TODO the other serial ports
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@ -89,13 +89,13 @@ class SamplerController(Module):
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control_block_addr_width = ceil(log2(num_channels + 1))
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# Bus address width
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addr_width = control_block_addr_width + sample_mem_addr_width
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addr_width = (num_channels + 1) * sample_mem_addr_width
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# "Master" bus
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self.bus = Interface(data_width=32, addr_width=addr_width)
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self.bus = Interface(data_width=32, adr_width=addr_width)
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# Wishbone bus used for mapping control registers
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self.control_regs_bus = Interface(data_width=32, addr_width=sample_mem_addr_width)
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self.control_regs_bus = Interface(data_width=32, adr_width=sample_mem_addr_width)
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slaves = []
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slaves.append((lambda adr: adr[sample_mem_addr_width:] == 0, self.control_regs_bus))
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@ -154,7 +154,7 @@ class SamplerController(Module):
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# Handle length values for each sample buffer
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for i, buffer in enumerate(self.buffers):
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cases.update({0x100 + i: rw_register(buffer.len, write=False)})
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cases.update({(0x100 >> 2) + i: rw_register(buffer.len, write=False)})
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# Connect up control registers bus
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self.sync += [
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@ -16,6 +16,7 @@ settings = {
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"gain": Settings.Gain,
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"center_frequency": Settings.CenterFreq,
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"sampling_enabled": Settings.SamplingEnabled,
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"trigger_run_len": Settings.TriggerRunLen,
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}
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@ -16,6 +16,7 @@ class Settings(IntEnum):
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Gain = 4
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CenterFreq = 5
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SamplingEnabled = 6
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TriggerRunLen = 7
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@dataclass
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