gateware: failed attempt to add my own peripheral to litex
moving to amaranth because it at least has API docs :(
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gateware/led_gpio.py
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14
gateware/led_gpio.py
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from migen import *
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from litex.soc.interconnect.csr import *
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from pathlib import Path
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class LedGpio(AutoCSR, Module):
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def __init__(self, platform, led: Signal):
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#source = Path(__file__).parent / "led_gpio.v"
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#platform.add_source(source)
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self.register = CSRStorage(8)
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self.comb += led.eq(self.register.storage[0])
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80
gateware/led_gpio.v
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80
gateware/led_gpio.v
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`default_nettype none
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module led_gpio #(
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parameter DATA_WIDTH = 32,
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parameter ADR_WIDTH = 32,
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parameter SEL_WIDTH = 4 // ???
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) (
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// Main signals
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input wire clk,
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input wire rst,
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// verilator lint_off UNUSED
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// ---- LiteX Wishbone interface
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// Address
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input wire [ADR_WIDTH-1:0] adr,
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// Data input (write)
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input wire [DATA_WIDTH-1:0] dat_w,
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// Data output (read)
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output reg [DATA_WIDTH-1:0] dat_r,
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// What parts of data are valid?
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input wire [SEL_WIDTH-1:0] sel,
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// Start cycle
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input wire cyc,
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// Enables wishbone interface
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input wire stb,
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// Bus cycle finished
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output reg ack,
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// Is this cycle a read or write?
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input wire we,
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// Cycle type
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input wire [2:0] cti,
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// Burst type
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input wire [1:0] bte,
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// Asserted if cycle completes with error
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output wire err,
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// verilator lint_on UNUSED
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// Output
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output wire led
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);
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// Tracks if we have started a new wishbone cycle. This or similar is needed so we don't
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// think we're handling multiple wishbone cycles inside one.
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reg cycle_started;
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reg led_state;
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always @(posedge clk) begin
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// Always reset the cycle started
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cycle_started <= 0;
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if (rst) begin
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led_state <= 0;
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end else begin
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// TODO ADR checking
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ack <= 0;
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err <= 0; // We never have any bus errors
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dat_r <= 0;
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if (!cycle_started && stb && cyc) begin
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cycle_started <= 1; // Start cycle to be reset next clock
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ack <= 1; // We always acknowledge immediately, we only take one clock to process
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if (we) begin
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// Writes to LED, so we need to assign output
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led_state <= dat_w[0];
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end else begin
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// We want reads to get LED status
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dat_r <= 3;
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end
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end
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end
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end
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always @(*) begin
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led = !led_state;
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end
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endmodule
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`default_nettype wire
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@ -15,11 +15,17 @@ from litex.soc.integration.builder import *
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from litex.soc.interconnect.csr import *
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from litex.soc.interconnect.csr import *
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from litex.soc.interconnect import wishbone
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from litex.soc.integration.soc import SoCRegion
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from litedram.modules import M12L64322A
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from litedram.modules import M12L64322A
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from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
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from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
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from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII
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from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII
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# My hardware
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import led_gpio
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# Module to configure clocks and resets
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# Module to configure clocks and resets
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class _CRG(Module):
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq, use_internal_osc=False, with_usb_pll=False, with_video_pll=False, sdram_rate="1:1"):
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def __init__(self, platform, sys_clk_freq, use_internal_osc=False, with_usb_pll=False, with_video_pll=False, sdram_rate="1:1"):
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@ -86,6 +92,10 @@ class _CRG(Module):
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# SoC definition - this basically instantiates hardware
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# SoC definition - this basically instantiates hardware
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class SoC(SoCCore):
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class SoC(SoCCore):
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csr_peripherals = ["led_gpio"]
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#csr_map_update(SoCCore.csr_map, csr_peripherals)
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# While there are more configurations in what I'm basing this off of, I'm reducing it to
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# While there are more configurations in what I'm basing this off of, I'm reducing it to
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# one supported config.
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# one supported config.
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def __init__(self, **kwargs):
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def __init__(self, **kwargs):
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@ -113,6 +123,19 @@ class SoC(SoCCore):
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l2_cache_size = 8192,
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l2_cache_size = 8192,
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)
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)
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# LED blinky thing
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#wb_interface = wishbone.Interface()
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led = platform.request("user_led_n")
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self.submodules.led_gpio = led_gpio.LedGpio(platform, led)
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#wb_interface.connect_to_pads(led, mode="slave")
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#self.add_memory_region("led_gpio", 0x8F000000, 0x1000, type="dawda")
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#self.add_wb_slave(0x8F000000, wb_interface, 0x1000)
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# vague attempt based on
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#region = SoCRegion(origin=0x8F000000, size=0x1000, cached=False)
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#self.bus.add_slave(name="led_gpio", slave=wb_interface, region=region)
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# TODO ethernet
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# TODO ethernet
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