81 lines
1.9 KiB
Verilog
81 lines
1.9 KiB
Verilog
`default_nettype none
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module led_gpio #(
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parameter DATA_WIDTH = 32,
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parameter ADR_WIDTH = 32,
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parameter SEL_WIDTH = 4 // ???
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) (
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// Main signals
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input wire clk,
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input wire rst,
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// verilator lint_off UNUSED
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// ---- LiteX Wishbone interface
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// Address
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input wire [ADR_WIDTH-1:0] adr,
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// Data input (write)
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input wire [DATA_WIDTH-1:0] dat_w,
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// Data output (read)
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output reg [DATA_WIDTH-1:0] dat_r,
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// What parts of data are valid?
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input wire [SEL_WIDTH-1:0] sel,
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// Start cycle
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input wire cyc,
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// Enables wishbone interface
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input wire stb,
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// Bus cycle finished
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output reg ack,
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// Is this cycle a read or write?
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input wire we,
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// Cycle type
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input wire [2:0] cti,
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// Burst type
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input wire [1:0] bte,
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// Asserted if cycle completes with error
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output wire err,
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// verilator lint_on UNUSED
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// Output
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output wire led
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);
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// Tracks if we have started a new wishbone cycle. This or similar is needed so we don't
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// think we're handling multiple wishbone cycles inside one.
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reg cycle_started;
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reg led_state;
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always @(posedge clk) begin
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// Always reset the cycle started
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cycle_started <= 0;
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if (rst) begin
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led_state <= 0;
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end else begin
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// TODO ADR checking
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ack <= 0;
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err <= 0; // We never have any bus errors
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dat_r <= 0;
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if (!cycle_started && stb && cyc) begin
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cycle_started <= 1; // Start cycle to be reset next clock
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ack <= 1; // We always acknowledge immediately, we only take one clock to process
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if (we) begin
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// Writes to LED, so we need to assign output
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led_state <= dat_w[0];
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end else begin
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// We want reads to get LED status
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dat_r <= 3;
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end
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end
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end
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end
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always @(*) begin
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led = !led_state;
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end
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endmodule
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`default_nettype wire
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