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fw: clean up some timer things in main

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This commit is contained in:
David Lenfesty 2023-06-16 16:33:07 -06:00
parent d4d119dc6e
commit afa95aa32e
1 changed files with 3 additions and 28 deletions
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31
firmware/src/main.rs
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@ -93,36 +93,17 @@ fn main() -> ! {
sock.set_timeout(Some(Duration::from_secs(10)))
}
let mut logger_tx_storage = [0u8; 128];
let mut logger_rx_storage = [0u8; 16];
let mut logger_tx_buf = SocketBuffer::new(&mut logger_tx_storage[..]);
let mut logger_rx_buf = SocketBuffer::new(&mut logger_rx_storage[..]);
let mut logger_socket = socket_set.add(TcpSocket::new(logger_tx_buf, logger_rx_buf));
unsafe {
logging::set_logger_socket(Some(socket_set.get_mut::<TcpSocket>(logger_socket)));
}
let mut last_blink: u32 = 0;
let mut toggle = false;
//defmt::info!("Done setup");
// Set up timer for polling events
unsafe {
//riscv::interrupt::enable();
//riscv::register::mie::set_mext();
//riscv::register::mie::set_msoft();
// Enable UART rx event for test
//write_reg(0xf000_4014, 1u32);
// Timer stuff
write_reg(0xf000_3808, 0u32); // Disable timer
write_reg(0xf000_3800, 0u32); // Set LOAD value
write_reg(0xf000_3804, 60_000_000u32); // Set RELOAD value
write_reg(0xf000_3808, 1u32); // Enable timer
// Enable timer event
//write_reg(0xf000_381c, 1u32);
}
let mut cmd = command_interface::CommandInterface::new();
@ -207,14 +188,8 @@ fn handle_timer_event() {
}
fn busy_wait(ms: u32) {
//let start = millis();
//while millis() - start < ms {
// unsafe {
// asm!("nop");
// }
//}
for i in 0..ms * 20_000 {
let start = millis();
while millis() - start < ms {
unsafe {
asm!("nop");
}