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gw: fix eth.py addressing issues

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This commit is contained in:
David Lenfesty 2023-04-22 18:38:26 -06:00
parent c0b293e0c7
commit c5db01c70f
3 changed files with 8 additions and 7 deletions
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1
firmware/Cargo.lock generated
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@ -105,6 +105,7 @@ dependencies = [
"defmt", "defmt",
"embedded-hal", "embedded-hal",
"panic-halt", "panic-halt",
"riscv",
"riscv-rt", "riscv-rt",
"smoltcp", "smoltcp",
] ]

1
firmware/Cargo.toml
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@ -7,6 +7,7 @@ edition = "2021"
[dependencies] [dependencies]
riscv-rt = "0.11.0" riscv-rt = "0.11.0"
riscv = "0.10.1"
panic-halt = "0.2.0" panic-halt = "0.2.0"
embedded-hal = "0.2.7" embedded-hal = "0.2.7"
defmt = {version = "0.3.4", features = ["encoding-raw"] } defmt = {version = "0.3.4", features = ["encoding-raw"] }

13
gateware/eth.py
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@ -2,6 +2,7 @@ from amaranth import *
from amaranth.lib.io import pin_layout from amaranth.lib.io import pin_layout
from amaranth_soc.wishbone.bus import Interface from amaranth_soc.wishbone.bus import Interface
from amaranth_soc.memory import MemoryMap from amaranth_soc.memory import MemoryMap
from math import log2, ceil
__all__ = ["LiteEth", "rgmii_layout"] __all__ = ["LiteEth", "rgmii_layout"]
@ -12,10 +13,11 @@ class LiteEth(Elaboratable, Interface):
def __init__(self, eth_interface): def __init__(self, eth_interface):
self.eth_interface = eth_interface self.eth_interface = eth_interface
# Addr width is 13 bits to accomodate 0x1FFF, which is well past what we care about # Highest address to support is 0x0002_1FFF, so need 18 bits of full address
Interface.__init__(self, addr_width=15, data_width=32, granularity=8, features=["cti", "bte", "err"]) highest_addr = 0x0002_1FFF
# TODO I need to understand the semantics here better bit_width = ceil(log2(highest_addr))
memory_map = MemoryMap(addr_width=17, data_width=8) Interface.__init__(self, addr_width=bit_width - 2, data_width=32, granularity=8, features=["cti", "bte", "err"])
memory_map = MemoryMap(addr_width=bit_width, data_width=8)
#memory_map.add_resource(self, name="LiteETH", size=0x2000) #memory_map.add_resource(self, name="LiteETH", size=0x2000)
self.memory_map = memory_map self.memory_map = memory_map
@ -31,7 +33,6 @@ class LiteEth(Elaboratable, Interface):
m = Module() m = Module()
# TODO I have to provide TX/RX clocks myself
core = Instance( core = Instance(
"liteeth_core", "liteeth_core",
i_sys_clock=ClockSignal(), i_sys_clock=ClockSignal(),
@ -81,8 +82,6 @@ rgmii_layout = [
("rst", pin_layout(1, "o")), ("rst", pin_layout(1, "o")),
("int_n", pin_layout(1, "i")), ("int_n", pin_layout(1, "i")),
# TODO is this not IO? why does LiteEth say input?
# I think the answer is it uses a primitive, not 100% right now
("mdio", pin_layout(1, "io")), ("mdio", pin_layout(1, "io")),
("mdc", pin_layout(1, "o")), ("mdc", pin_layout(1, "o")),
("rx_ctl", pin_layout(1, "i")), ("rx_ctl", pin_layout(1, "i")),