gw: fix eth.py addressing issues

firmware/Cargo.lock

@@ -105,6 +105,7 @@ dependencies = [
  "defmt",
  "embedded-hal",
  "panic-halt",
+ "riscv",
  "riscv-rt",
  "smoltcp",
 ]

firmware/Cargo.toml

@@ -7,6 +7,7 @@ edition = "2021"
 
 [dependencies]
 riscv-rt = "0.11.0"
+riscv = "0.10.1"
 panic-halt = "0.2.0"
 embedded-hal = "0.2.7"
 defmt = {version = "0.3.4", features = ["encoding-raw"] }

gateware/eth.py

@@ -2,6 +2,7 @@ from amaranth import *
 from amaranth.lib.io import pin_layout
 from amaranth_soc.wishbone.bus import Interface
 from amaranth_soc.memory import MemoryMap
+from math import log2, ceil
 
 
 __all__ = ["LiteEth", "rgmii_layout"]
@@ -12,10 +13,11 @@ class LiteEth(Elaboratable, Interface):
     def __init__(self, eth_interface):
         self.eth_interface = eth_interface
 
-        # Addr width is 13 bits to accomodate 0x1FFF, which is well past what we care about
-        Interface.__init__(self, addr_width=15, data_width=32, granularity=8, features=["cti", "bte", "err"])
-        # TODO I need to understand the semantics here better
-        memory_map = MemoryMap(addr_width=17, data_width=8)
+        # Highest address to support is 0x0002_1FFF, so need 18 bits of full address
+        highest_addr = 0x0002_1FFF
+        bit_width = ceil(log2(highest_addr))
+        Interface.__init__(self, addr_width=bit_width - 2, data_width=32, granularity=8, features=["cti", "bte", "err"])
+        memory_map = MemoryMap(addr_width=bit_width, data_width=8)
         #memory_map.add_resource(self, name="LiteETH", size=0x2000)
         self.memory_map = memory_map
 
@@ -31,7 +33,6 @@ class LiteEth(Elaboratable, Interface):
         m = Module()
 
 
-        # TODO I have to provide TX/RX clocks myself
         core = Instance(
             "liteeth_core",
             i_sys_clock=ClockSignal(),
@@ -81,8 +82,6 @@ rgmii_layout = [
     ("rst", pin_layout(1, "o")),
     ("int_n", pin_layout(1, "i")),
 
-    # TODO is this not IO? why does LiteEth say input?
-    # I think the answer is it uses a primitive, not 100% right now
     ("mdio", pin_layout(1, "io")),
     ("mdc", pin_layout(1, "o")),
     ("rx_ctl", pin_layout(1, "i")),