gateware: name submodules properly and start fleshing out CLI
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@ -6,10 +6,11 @@ from amaranth_boards import colorlight_i9
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from amaranth_soc.wishbone import Interface, Arbiter, Decoder
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from amaranth_soc.memory import MemoryMap
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from typing import List
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from minerva.core import Minerva
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from typing import List
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from argparse import ArgumentParser
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class Blinky(Elaboratable):
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def __init__(self):
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self.count = Signal(64)
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@ -157,6 +158,7 @@ class LEDPeripheral(Elaboratable, Interface):
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return m
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# TODO clean this up, generate binary here, maybe even run cargo build
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def load_firmware_for_mem() -> List[int]:
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with open('../firmware/fw.bin', 'rb') as f:
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# Stored as little endian, LSB first??
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@ -178,9 +180,9 @@ class Core(Elaboratable):
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def elaborate(self, platform):
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m = Module()
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m.submodules += self.cpu
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m.submodules += self.arbiter
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m.submodules += self.decoder
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m.submodules.cpu = self.cpu
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m.submodules.arbiter = self.arbiter
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m.submodules.decoder = self.decoder
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# Connect ibus and dbus together for simplicity for now
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minerva_wb_features = ["cti", "bte", "err"]
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@ -210,24 +212,22 @@ class Core(Elaboratable):
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fw = load_firmware_for_mem()
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print(len(fw))
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print(fw)
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# Hook up memory space
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self.rom = ROM(fw)
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m.submodules += self.rom
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m.submodules.rom = self.rom
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# Problem: not sure to handle how we do byte vs word addressing properly
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# So doing this shift is a bit of a hacky way to impl anything
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start, _stop, _step = self.decoder.add(self.rom, addr=(0x01000000 >> 2))
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print(f"ROM added at 0x{start:08x}")
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self.ram = RAM()
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m.submodules += self.ram
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m.submodules.ram = self.ram
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start, _stop, _step = self.decoder.add(self.ram)
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print(f"RAM added at 0x{start:08x}")
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self.led = LEDPeripheral(self.led_signal)
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m.submodules += self.led
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m.submodules.led = self.led
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start, _stop, _step = self.decoder.add(self.led)
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print(f"LED added at 0x{start:08x}")
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@ -251,11 +251,12 @@ class SoC(Elaboratable):
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led_signal = platform.request("led")
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core = Core(led_signal)
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m.submodules += core
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m.submodules.core = core
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return m
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# TODO add more harnessing
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class TestDevice(Elaboratable):
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def __init__(self):
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pass
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@ -265,10 +266,11 @@ class TestDevice(Elaboratable):
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m = Module()
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led_signal = Signal()
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core = Core(led_signal)
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m.submodules += core
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m.submodules.core = core
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return m
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# TODO add structure to add regression tests
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def run_sim():
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dut = TestDevice()
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sim = Simulator(dut)
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@ -285,6 +287,17 @@ def run_sim():
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if __name__ == "__main__":
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colorlight_i9.Colorlight_i9_Platform().build(SoC(), debug_verilog=True)
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args = ArgumentParser(description="ARVP Sonar Acquisition FPGA gateware.")
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args.add_argument("--build", action="store_true", help="Build bitstream.")
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args.add_argument("--gen-debug-verilog", action="store_true", help="Save debug verilog.")
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# TODO maybe allow an optional arg to specify an individual test to run?
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args.add_argument("--test", action="store_true", help="Run RTL test suite and report results.")
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args.add_argument("--save-vcd", action="store_true", help="Save VCD waveforms from test(s).")
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args = args.parse_args()
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#run_sim()
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if args.build:
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colorlight_i9.Colorlight_i9_Platform().build(SoC(), debug_verilog=args.gen_debug_verilog)
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if args.test:
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# TODO pass save_vcd arg through
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run_sim()
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