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gateware: name submodules properly and start fleshing out CLI

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This commit is contained in:
David Lenfesty 2023-01-22 20:25:39 -07:00
parent 446db81464
commit cf1c129054
1 changed files with 27 additions and 14 deletions
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41
gateware/soc.py
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@ -6,10 +6,11 @@ from amaranth_boards import colorlight_i9
from amaranth_soc.wishbone import Interface, Arbiter, Decoder from amaranth_soc.wishbone import Interface, Arbiter, Decoder
from amaranth_soc.memory import MemoryMap from amaranth_soc.memory import MemoryMap
from typing import List
from minerva.core import Minerva from minerva.core import Minerva
from typing import List
from argparse import ArgumentParser
class Blinky(Elaboratable): class Blinky(Elaboratable):
def __init__(self): def __init__(self):
self.count = Signal(64) self.count = Signal(64)
@ -157,6 +158,7 @@ class LEDPeripheral(Elaboratable, Interface):
return m return m
# TODO clean this up, generate binary here, maybe even run cargo build
def load_firmware_for_mem() -> List[int]: def load_firmware_for_mem() -> List[int]:
with open('../firmware/fw.bin', 'rb') as f: with open('../firmware/fw.bin', 'rb') as f:
# Stored as little endian, LSB first?? # Stored as little endian, LSB first??
@ -178,9 +180,9 @@ class Core(Elaboratable):
def elaborate(self, platform): def elaborate(self, platform):
m = Module() m = Module()
m.submodules += self.cpu m.submodules.cpu = self.cpu
m.submodules += self.arbiter m.submodules.arbiter = self.arbiter
m.submodules += self.decoder m.submodules.decoder = self.decoder
# Connect ibus and dbus together for simplicity for now # Connect ibus and dbus together for simplicity for now
minerva_wb_features = ["cti", "bte", "err"] minerva_wb_features = ["cti", "bte", "err"]
@ -210,24 +212,22 @@ class Core(Elaboratable):
fw = load_firmware_for_mem() fw = load_firmware_for_mem()
print(len(fw))
print(fw)
# Hook up memory space # Hook up memory space
self.rom = ROM(fw) self.rom = ROM(fw)
m.submodules += self.rom m.submodules.rom = self.rom
# Problem: not sure to handle how we do byte vs word addressing properly # Problem: not sure to handle how we do byte vs word addressing properly
# So doing this shift is a bit of a hacky way to impl anything # So doing this shift is a bit of a hacky way to impl anything
start, _stop, _step = self.decoder.add(self.rom, addr=(0x01000000 >> 2)) start, _stop, _step = self.decoder.add(self.rom, addr=(0x01000000 >> 2))
print(f"ROM added at 0x{start:08x}") print(f"ROM added at 0x{start:08x}")
self.ram = RAM() self.ram = RAM()
m.submodules += self.ram m.submodules.ram = self.ram
start, _stop, _step = self.decoder.add(self.ram) start, _stop, _step = self.decoder.add(self.ram)
print(f"RAM added at 0x{start:08x}") print(f"RAM added at 0x{start:08x}")
self.led = LEDPeripheral(self.led_signal) self.led = LEDPeripheral(self.led_signal)
m.submodules += self.led m.submodules.led = self.led
start, _stop, _step = self.decoder.add(self.led) start, _stop, _step = self.decoder.add(self.led)
print(f"LED added at 0x{start:08x}") print(f"LED added at 0x{start:08x}")
@ -251,11 +251,12 @@ class SoC(Elaboratable):
led_signal = platform.request("led") led_signal = platform.request("led")
core = Core(led_signal) core = Core(led_signal)
m.submodules += core m.submodules.core = core
return m return m
# TODO add more harnessing
class TestDevice(Elaboratable): class TestDevice(Elaboratable):
def __init__(self): def __init__(self):
pass pass
@ -265,10 +266,11 @@ class TestDevice(Elaboratable):
m = Module() m = Module()
led_signal = Signal() led_signal = Signal()
core = Core(led_signal) core = Core(led_signal)
m.submodules += core m.submodules.core = core
return m return m
# TODO add structure to add regression tests
def run_sim(): def run_sim():
dut = TestDevice() dut = TestDevice()
sim = Simulator(dut) sim = Simulator(dut)
@ -285,6 +287,17 @@ def run_sim():
if __name__ == "__main__": if __name__ == "__main__":
colorlight_i9.Colorlight_i9_Platform().build(SoC(), debug_verilog=True) args = ArgumentParser(description="ARVP Sonar Acquisition FPGA gateware.")
args.add_argument("--build", action="store_true", help="Build bitstream.")
args.add_argument("--gen-debug-verilog", action="store_true", help="Save debug verilog.")
# TODO maybe allow an optional arg to specify an individual test to run?
args.add_argument("--test", action="store_true", help="Run RTL test suite and report results.")
args.add_argument("--save-vcd", action="store_true", help="Save VCD waveforms from test(s).")
args = args.parse_args()
#run_sim() if args.build:
colorlight_i9.Colorlight_i9_Platform().build(SoC(), debug_verilog=args.gen_debug_verilog)
if args.test:
# TODO pass save_vcd arg through
run_sim()