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gw: minor fixes for correct controller operation

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This commit is contained in:
David Lenfesty 2023-05-27 12:08:12 -06:00
parent 627550840c
commit e624d82742
2 changed files with 10 additions and 8 deletions
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2
gateware/sampler/circular_buffer.py
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@ -21,7 +21,7 @@ class CircularBuffer(Module):
ptr_width = ceil(log2(depth)) ptr_width = ceil(log2(depth))
# External Signals # External Signals
self.len = Signal(ptr_width) # Amount of valid data in the buffer self.len = Signal(ptr_width + 1) # Amount of valid data in the buffer
self.clear = Signal() # Strobe to clear memory self.clear = Signal() # Strobe to clear memory
self.rd_addr = Signal(ptr_width) self.rd_addr = Signal(ptr_width)
self.rd_data = Signal(width) self.rd_data = Signal(width)

16
gateware/sampler/controller.py
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@ -31,7 +31,7 @@ class SamplerController(Module):
Bit 0 - Begin capture. Resets all FIFOs and starts the peak detector Bit 0 - Begin capture. Resets all FIFOs and starts the peak detector
0x01: Status Register (RO) 0x01: Status Register (RO)
Bit 0 - Capture complete. Set by peak detection block and cleared by software or when Bit 0 - Capture complete. Set by peak detection block and cleared when capture is began
0x02: trigger_run_len (RW) 0x02: trigger_run_len (RW)
Number of samples to acquire after triggering sample. Number of samples to acquire after triggering sample.
@ -67,6 +67,9 @@ class SamplerController(Module):
# Connect each buffer to each sampler # Connect each buffer to each sampler
for buffer, sampler in zip(self.buffers, self.samplers): for buffer, sampler in zip(self.buffers, self.samplers):
self.submodules += buffer
self.submodules += sampler
self.comb += [ self.comb += [
# Connect only top 9 bits to memory # Connect only top 9 bits to memory
buffer.wr_data.eq(sampler.data[1:]), buffer.wr_data.eq(sampler.data[1:]),
@ -76,8 +79,9 @@ class SamplerController(Module):
# Each sampler gets some chunk of memory at least large enough to fit # Each sampler gets some chunk of memory at least large enough to fit
# all of it's data, so use that as a consistent offset # all of it's data, so use that as a consistent offset. Use a minimum
sample_mem_addr_width = ceil(log2(buffer_len)) # address of 0x800 to avoid conflicts with control registers
sample_mem_addr_width = max(ceil(log2(buffer_len)), ceil(log2(0x800)))
# 1 control block + number of channels used = control bits # 1 control block + number of channels used = control bits
control_block_addr_width = ceil(log2(num_channels + 1)) control_block_addr_width = ceil(log2(num_channels + 1))
@ -100,11 +104,9 @@ class SamplerController(Module):
adr = (i + 1) << sample_mem_addr_width adr = (i + 1) << sample_mem_addr_width
print(f"Sampler {i} available at 0x{adr:08x}") print(f"Sampler {i} available at 0x{adr:08x}")
self.decoder = Decoder(self.bus, slaves) self.submodules.decoder = Decoder(self.bus, slaves)
# TODO how to submodule
self.submodules.decoder = self.decoder
self.peak_detector = PeakDetector(10) self.submodules.peak_detector = PeakDetector(10)
self.comb += [ self.comb += [
# Simply enable whenever we start capturing # Simply enable whenever we start capturing
self.peak_detector.enable.eq(sample_enable), self.peak_detector.enable.eq(sample_enable),