hw: fix silkscreen issue

firmware/build_and_strip.sh

@@ -2,7 +2,8 @@
 DEFMT_LOG=debug cargo build --release
 if [ $? -ne 0 ]
 then
-    exit $?
+    # Can't use $? because the check itself also updates the return code
+    exit 1
 fi
 
 # Account for different toolchains

firmware/src/main.rs

@@ -32,6 +32,7 @@ mod logging;
 mod mcp4726;
 mod proto;
 mod uart;
+mod sampler;
 
 const MAC: [u8; 6] = [0xA0, 0xBB, 0xCC, 0xDD, 0xEE, 0xF0];
 
@@ -93,6 +94,18 @@ fn main() -> ! {
         sock.set_timeout(Some(Duration::from_secs(10)))
     }
 
+    let mut data_tx_storage = [0u8; 256];
+    let mut data_rx_storage = [0u8; 24];
+    let mut data_tx_buf = SocketBuffer::new(&mut data_tx_storage[..]);
+    let mut data_rx_buf = SocketBuffer::new(&mut data_rx_storage[..]);
+    let mut data_socket = socket_set.add(TcpSocket::new(data_tx_buf, data_rx_buf));
+    {
+        let mut sock = socket_set.get_mut::<TcpSocket>(data_socket);
+        // TODO these values are obscene, should fix the underlying bug
+        sock.set_keep_alive(Some(Duration::from_secs(2)));
+        sock.set_timeout(Some(Duration::from_secs(10)))
+    }
+
     let mut last_blink: u32 = 0;
     let mut toggle = false;
     //defmt::info!("Done setup");
@@ -110,23 +123,41 @@ fn main() -> ! {
 
     loop {
         let now = millis();
+        iface.poll(Instant::from_millis(now), &mut device, &mut socket_set);
+
+        // TODO first connection to a socket takes a while to establish, and can time out, why?
+        cmd.run(socket_set.get_mut(command_socket));
+
         // TODO the need for the second check screams something is unsound somewhere
         if now - last_blink > 1000 && now > last_blink {
             last_blink = now;
             toggle = !toggle;
             write_led(if toggle { 1 } else { 0 });
 
-            let val: u32 = unsafe { read_reg(0x8000_2000) };
+            let mut sock = socket_set.get_mut::<TcpSocket>(data_socket);
+            if !sock.is_open() {
+                sock.listen(3000);
+            }
+
+            if toggle {
+                sampler::clear_buffers();
+                sampler::start_sampling();
+
+                let buf = unsafe {sampler::get_sample_buffer(0) };
+                let status = sampler::read_status();
+                let raw_reg: u32 = unsafe { read_reg(0x8040_0004) };
+                defmt::debug!("Start: len: {}, complete: {}, running: {}, status: {}", buf.len(), status.capture_complete, status.sampling, raw_reg);
+            } else {
+                sampler::stop_sampling();
+                let buf = unsafe {sampler::get_sample_buffer(0) };
+                defmt::debug!("Stopped, len: {}", buf.len());
+            }
         }
 
         // TODO I think the timer might actually stop until the event is cleared? this may pose
         // problems, might explain why moving this above the smoltcp stuff "broke" things
         handle_timer_event();
 
-        iface.poll(Instant::from_millis(now), &mut device, &mut socket_set);
-
-        // TODO first connection to a socket takes a while to establish, and can time out, why?
-        cmd.run(socket_set.get_mut(command_socket));
     }
 }
 

firmware/src/proto.rs

@@ -53,6 +53,8 @@ pub enum Settings {
     CenterFreq = 5,
     /// Sampling enabled, 1 to enable, 0 to disable
     SamplingEnabled = 6,
+    /// Number of samples acquired after trigger
+    TriggerRunLen = 7,
 }
 
 #[derive(Clone, Copy, Debug)]

gateware/litex_main.py

@@ -146,7 +146,7 @@ class BaseSoC(SoCCore):
         samplers = [Sampler(platform.request("adc", i)) for i in range(3)]
         self.submodules.sampler_controller = SamplerController(samplers, buffer_len=2048 * 10)
         # TODO better way to do this?
-        sampler_region = SoCRegion(origin=None, size=0x4000, cached=False)
+        sampler_region = SoCRegion(origin=None, size=0x0040_0000, cached=False)
         self.bus.add_slave(name="sampler", slave=self.sampler_controller.bus, region=sampler_region)
 
 # Build --------------------------------------------------------------------------------------------

gateware/platforms/sonar.py

@@ -27,11 +27,16 @@ _io_v7_0 = [ # Colorlight i9 documented by @smunaut
     ("user_led_n", 0, Pins("U16"), IOStandard("LVCMOS33")),
 
     # Serial
-    ("serial", 0,
+    ("serial", 2,
         Subsignal("tx", Pins("P16")),
         Subsignal("rx", Pins("L5")),
         IOStandard("LVCMOS33")
     ),
+    ("serial", 3,
+        Subsignal("tx", Pins("J18")),
+        Subsignal("rx", Pins("J16")),
+        IOStandard("LVCMOS33")
+    ),
 
     # TODO the other serial ports
 

gateware/sampler/controller.py

@@ -89,13 +89,13 @@ class SamplerController(Module):
         control_block_addr_width = ceil(log2(num_channels + 1))
 
         # Bus address width
-        addr_width = control_block_addr_width + sample_mem_addr_width
+        addr_width = (num_channels + 1) * sample_mem_addr_width
 
         # "Master" bus
-        self.bus = Interface(data_width=32, addr_width=addr_width)
+        self.bus = Interface(data_width=32, adr_width=addr_width)
 
         # Wishbone bus used for mapping control registers
-        self.control_regs_bus = Interface(data_width=32, addr_width=sample_mem_addr_width)
+        self.control_regs_bus = Interface(data_width=32, adr_width=sample_mem_addr_width)
 
         slaves = []
         slaves.append((lambda adr: adr[sample_mem_addr_width:] == 0, self.control_regs_bus))
@@ -154,7 +154,7 @@ class SamplerController(Module):
 
         # Handle length values for each sample buffer
         for i, buffer in enumerate(self.buffers):
-            cases.update({0x100 + i: rw_register(buffer.len, write=False)})
+            cases.update({(0x100 >> 2) + i: rw_register(buffer.len, write=False)})
 
         # Connect up control registers bus
         self.sync += [

hardware/colorlight-base/colorlight-base.kicad_pcb

@@ -9372,7 +9372,7 @@
     (property "ki_keywords" "capacitor cap")
     (path "/a344e32e-f890-42e3-bec8-9a384cb1a4dc/4c3e582c-dee4-4ebb-a1e9-7c647c777882")
     (attr smd)
-    (fp_text reference "C405" (at -4.2 1.95) (layer "B.SilkS")
+    (fp_text reference "C405" (at -4.2 0.05) (layer "B.SilkS")
         (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
       (tstamp 35038e28-f925-4001-a5d6-c89a9bfdfcb3)
     )
@@ -9836,7 +9836,7 @@
     (property "ki_keywords" "R res resistor")
     (path "/a344e32e-f890-42e3-bec8-9a384cb1a4dc/048d1ca6-5643-4c50-acf7-be4ef6123b63")
     (attr smd)
-    (fp_text reference "R411" (at 4.15 1.7) (layer "B.SilkS")
+    (fp_text reference "R411" (at 4.1 0.05) (layer "B.SilkS")
         (effects (font (size 1 1) (thickness 0.15)) (justify mirror))
       (tstamp 202b92a1-073f-4d42-8b9b-02a12bc9870e)
     )
@@ -11389,10 +11389,10 @@
   (segment (start 81.950499 65.950499) (end 80.950499 64.950499) (width 0.25) (layer "F.Cu") (net 45) (tstamp bfb83895-526e-49b7-afd5-47f20a76eb0e))
   (segment (start 82.450499 64.449501) (end 84 62.9) (width 0.25) (layer "F.Cu") (net 46) (tstamp 07475a4d-7ff0-4253-b82a-fbd03d5bbed3))
   (segment (start 84 62.9) (end 84 39.84) (width 0.25) (layer "F.Cu") (net 46) (tstamp 4057a98f-9d20-4de0-a859-ef8416263c8e))
-  (segment (start 56.553 95.448) (end 77.28062 95.448) (width 0.25) (layer "F.Cu") (net 46) (tstamp 9d2b9f82-54ce-4f18-806e-a0305b60ce23))
   (segment (start 84 39.84) (end 87.63 36.21) (width 0.25) (layer "F.Cu") (net 46) (tstamp a2dafef0-1c9e-4bd3-9d92-21a5bfe74ba3))
   (segment (start 82.450499 90.278121) (end 82.450499 64.449501) (width 0.25) (layer "F.Cu") (net 46) (tstamp b053f040-3e6e-48b6-8858-f7c0d75822f4))
   (segment (start 77.28062 95.448) (end 82.450499 90.278121) (width 0.25) (layer "F.Cu") (net 46) (tstamp f6db9b9b-5713-42db-8c23-3ed18d7ec529))
+  (segment (start 56.553 95.448) (end 35.82538 95.448) (width 0.25) (layer "B.Cu") (net 46) (tstamp 9d2b9f82-54ce-4f18-806e-a0305b60ce23))
   (segment (start 82.9 90.46431) (end 82.9 64.63569) (width 0.25) (layer "F.Cu") (net 47) (tstamp 3115ef43-9e33-4ff1-8366-296bdf225139))
   (segment (start 84.449501 41.930499) (end 87.63 38.75) (width 0.25) (layer "F.Cu") (net 47) (tstamp 53948adc-8094-409d-83df-a734cdbc0e42))
   (segment (start 56.553 96.048) (end 77.31631 96.048) (width 0.25) (layer "F.Cu") (net 47) (tstamp 717b076e-a419-485a-888f-eb81344c2e5b))

pysonar/__init__.py

@@ -16,6 +16,7 @@ settings = {
     "gain": Settings.Gain,
     "center_frequency": Settings.CenterFreq,
     "sampling_enabled": Settings.SamplingEnabled,
+    "trigger_run_len": Settings.TriggerRunLen,
 }
 
 

pysonar/command_packets.py

@@ -16,6 +16,7 @@ class Settings(IntEnum):
     Gain = 4
     CenterFreq = 5
     SamplingEnabled = 6
+    TriggerRunLen = 7
 
 
 @dataclass