fw: start janky ethernet bringup testing

This was causing my nextpnr crash. I really do need to figure out how to
do this in a less hacky way. Or even just make it more explicit that I
am doing this for a reason.

firmware/src/eth.rs

@@ -0,0 +1,41 @@
+//! Quick and hacky ethernet thing to test
+
+const LITEETH_BASE: u32 = 0x0050_0000;
+
+
+const ETHMAC_SRAM_WRITER_EV_PENDING: u32 = LITEETH_BASE + 0x810;
+const ETHMAC_SRAM_WRITER_EV_ENABLE: u32 = LITEETH_BASE + 0x814;
+const ETHMAC_SRAM_READER_EV_PENDING: u32 = LITEETH_BASE + 0x830;
+const ETHMAC_SRAM_READER_EV_ENABLE: u32 = LITEETH_BASE + 0x834;
+
+fn write_u32_reg(addr: u32, value: u32) {
+    unsafe { *(addr as *mut u32) = value; }
+}
+
+fn read_u32_reg(addr: u32) -> u32 {
+    unsafe {
+        return *(addr as *mut u32);
+    }
+}
+
+pub fn is_wishbone_correct() -> bool {
+    let value = read_u32_reg(LITEETH_BASE + 4);
+
+    // If this isn't true, we screwed.
+    return value == 0x12345678;
+}
+
+pub fn init() {
+    // Clear any potential pending events
+    write_u32_reg(ETHMAC_SRAM_WRITER_EV_PENDING, 1);
+    write_u32_reg(ETHMAC_SRAM_READER_EV_PENDING, 1);
+
+    // Disable all events
+    write_u32_reg(ETHMAC_SRAM_WRITER_EV_ENABLE, 0);
+    write_u32_reg(ETHMAC_SRAM_READER_EV_ENABLE, 0);
+}
+
+pub fn tranmsit() {
+
+}
+

firmware/src/main.rs

@@ -7,17 +7,28 @@ use core::{arch::asm, ptr::write};
 
 use riscv_rt::entry;
 
+mod eth;
+
 // use `main` as the entry point of this application
 // `main` is not allowed to return
 #[entry]
 fn main() -> ! {
+    //eth::init();
+
+    let blink_period = if eth::is_wishbone_correct() {
+        10_000_000
+    } else {
+        500_000
+    };
+
+
     // do something here
     loop {
         unsafe {
             write(0x01002000 as *mut u32, 0);
-            busy_wait(10_000_000);
+            busy_wait(blink_period);
             write(0x01002000 as *mut u32, 1);
-            busy_wait(10_000_000);
+            busy_wait(blink_period);
         }
     }
 }

gateware/eth.py

@@ -1,6 +1,7 @@
 from amaranth import *
 from amaranth.lib.io import pin_layout
 from amaranth_soc.wishbone.bus import Interface
+from amaranth_soc.memory import MemoryMap
 
 
 __all__ = ["LiteEth", "rgmii_layout"]
@@ -8,12 +9,15 @@ __all__ = ["LiteEth", "rgmii_layout"]
 
 # TODO maybe this should just call liteeth_gen to close the loop?
 class LiteEth(Elaboratable, Interface):
-    def __init__(self):
+    def __init__(self, eth_interface):
+        self.eth_interface = eth_interface
 
         # Addr width is 13 bits to accomodate 0x1FFF, which is well p
         Interface.__init__(self, addr_width=13, data_width=32, granularity=8, features=["cti", "bte", "err"])
-
+        # TODO I need to understand the semantics here better
-        self.rgmii_eth_clocks_tx = Signal()
+        memory_map = MemoryMap(addr_width=15, data_width=8)
+        #memory_map.add_resource(self, name="LiteETH", size=0x2000)
+        self.memory_map = memory_map
 
         self.interrupt = Signal()
 
@@ -32,7 +36,17 @@ class LiteEth(Elaboratable, Interface):
             i_sys_clock=ClockSignal(),
 
             # RGMII signals
-            o_rgmii_eth_clocks_tx=self.rgmii_eth_clocks_tx,
+            o_rgmii_eth_clocks_tx=self.eth_interface.tx_clk,
+            i_rgmii_eth_clocks_rx=self.eth_interface.rx_clk,
+            o_rgmii_eth_rst_n=self.eth_interface.rst,
+            i_rgmii_eth_int_n=Const(1),
+            # TODO actually fix the platform to support this problem.
+            #i_rgmii_eth_mdio=self.eth_interface.mdio,
+            o_rgmii_eth_mdc=self.eth_interface.mdc,
+            i_rgmii_eth_rx_ctl=self.eth_interface.rx_ctl,
+            i_rgmii_eth_rx_data=self.eth_interface.rx_data,
+            o_rgmii_eth_tx_ctl=self.eth_interface.tx_ctl,
+            o_rgmii_eth_tx_data=self.eth_interface.tx_data,
 
             # Wishbone all the things
             i_wishbone_adr=self.adr,
@@ -49,15 +63,17 @@ class LiteEth(Elaboratable, Interface):
             o_interrupt=self.interrupt,
         )
 
+        # TODO connect ethernet interface
+
         m.submodules.core = core
 
         return m
 
 
 rgmii_layout = [
-    ("clocks_tx", pin_layout(1, "o")),
+    ("tx_clk", pin_layout(1, "o")),
-    ("clocks_rx", pin_layout(1, "i")),
+    ("rx_clk", pin_layout(1, "i")),
-    ("rst_n", pin_layout(1, "o")),
+    ("rst", pin_layout(1, "o")),
     ("int_n", pin_layout(1, "i")),
 
     # TODO is this not IO? why does LiteEth say input?

gateware/gen_pll.sh

@@ -0,0 +1,3 @@
+#!/usr/bin/env sh
+
+ecppll --clkin 25 --clkout0 50 --clkout1 10 -f pll.v

gateware/main.py

@@ -39,12 +39,14 @@ def load_firmware_for_mem() -> List[int]:
         return out
 
 class Core(Elaboratable):
-    def __init__(self, led_signal):
+    def __init__(self, clk25, led_signal, eth_interface):
         self.count = Signal(64)
         self.cpu = Minerva(reset_address=0x01000000)
         self.arbiter = Arbiter(addr_width=32, data_width=32)
-        self.decoder = Decoder(addr_width=32, data_width=32)
+        self.decoder = Decoder(addr_width=32, data_width=32, features=["err"])
+        self.clk25 = clk25
         self.led_signal = led_signal
+        self.eth_interface = eth_interface
 
     def elaborate(self, platform):
         m = Module()
@@ -52,6 +54,29 @@ class Core(Elaboratable):
         m.submodules.arbiter = self.arbiter
         m.submodules.decoder = self.decoder
 
+        # Create main and sampling clock, using PLL and 25MHz input clock
+        platform.add_file("pll.v", open("pll.v", "r").read())
+        sys_clk = Signal()
+        sample_clk = Signal()
+        pll = Instance(
+            "pll",
+            i_clkin=self.clk25,
+            o_clkout0=sys_clk,
+            o_clkout1=sample_clk,
+        )
+        m.submodules.pll = pll
+
+        # Create new clock domains
+        m.domains += ClockDomain("sync")
+        m.domains += ClockDomain("sample")
+        m.d.comb += ClockSignal("sync").eq(sys_clk)
+        m.d.comb += ClockSignal("sample").eq(sample_clk)
+
+        # Add clock constraints
+        if platform is not None:
+            platform.add_clock_constraint(sys_clk, 50e6)
+            platform.add_clock_constraint(sample_clk, 10e6)
+
         # Connect ibus and dbus together for simplicity for now
         minerva_wb_features = ["cti", "bte", "err"]
         self.ibus = Interface(addr_width=32, data_width=32, features=minerva_wb_features)
@@ -99,13 +124,16 @@ class Core(Elaboratable):
         start, _stop, _step = self.decoder.add(self.led)
         print(f"LED added at 0x{start:08x}")
 
-        # Connect arbiter to decoder
-        m.d.comb += self.arbiter.bus.connect(self.decoder.bus)
-
         m.submodules.uart = uart.UART(10e6)
 
         # Ethernet
-        m.submodules.eth = LiteEth()
+        self.eth = LiteEth(self.eth_interface)
+        m.submodules.eth = self.eth
+        start, _stop, _step = self.decoder.add(self.eth, addr=0x00500000)
+        print(f"LiteETH added at 0x{start:08x}")
+
+        # Connect arbiter to decoder
+        m.d.comb += self.arbiter.bus.connect(self.decoder.bus)
 
         # Counter
         #m.d.sync += self.count.eq(self.count + 1)
@@ -121,12 +149,16 @@ class SoC(Elaboratable):
 
     def elaborate(self, platform):
         if platform is not None:
+            clk25 = platform.request("clk25")
             led_signal = platform.request("led")
+            ethernet_interface = platform.request("eth_rgmii", 1)
         else:
             # platform is None in simulation, so provide harnesses for required signals
+            clk25 = Signal() # TODO unsure if this will work in sim
             led_signal = Signal()
+            ethernet_interface = Record(rgmii_layout)
 
-        return Core(led_signal)
+        return Core(clk25, led_signal, ethernet_interface)
 
 
 # TODO add structure to add regression tests
@@ -155,7 +187,9 @@ if __name__ == "__main__":
     args = args.parse_args()
 
     if args.build:
-        colorlight_i9.Colorlight_i9_Platform().build(SoC(), debug_verilog=args.gen_debug_verilog)
+        # Overrides are available via AMARANTH_<override_variable_name> env variable, or kwarg
+        # TODO fix platform so I don't have to manually specify MDIO signal
+        colorlight_i9.Colorlight_i9_Platform().build(SoC(), debug_verilog=args.gen_debug_verilog, nextpnr_opts="--router router1", add_preferences="LOCATE COMP \"top.eth.core.rgmii_eth_mdio\" SITE \"P5\";\n")
 
     if args.test:
         if args.save_vcd:

gateware/pll.v

@@ -0,0 +1,53 @@
+// diamond 3.7 accepts this PLL
+// diamond 3.8-3.9 is untested
+// diamond 3.10 or higher is likely to abort with error about unable to use feedback signal
+// cause of this could be from wrong CPHASE/FPHASE parameters
+module pll
+(
+    input clkin, // 25 MHz, 0 deg
+    output clkout0, // 50 MHz, 0 deg
+    output clkout1, // 10 MHz, 0 deg
+    output locked
+);
+(* FREQUENCY_PIN_CLKI="25" *)
+(* FREQUENCY_PIN_CLKOP="50" *)
+(* FREQUENCY_PIN_CLKOS="10" *)
+(* ICP_CURRENT="12" *) (* LPF_RESISTOR="8" *) (* MFG_ENABLE_FILTEROPAMP="1" *) (* MFG_GMCREF_SEL="2" *)
+EHXPLLL #(
+        .PLLRST_ENA("DISABLED"),
+        .INTFB_WAKE("DISABLED"),
+        .STDBY_ENABLE("DISABLED"),
+        .DPHASE_SOURCE("DISABLED"),
+        .OUTDIVIDER_MUXA("DIVA"),
+        .OUTDIVIDER_MUXB("DIVB"),
+        .OUTDIVIDER_MUXC("DIVC"),
+        .OUTDIVIDER_MUXD("DIVD"),
+        .CLKI_DIV(1),
+        .CLKOP_ENABLE("ENABLED"),
+        .CLKOP_DIV(12),
+        .CLKOP_CPHASE(5),
+        .CLKOP_FPHASE(0),
+        .CLKOS_ENABLE("ENABLED"),
+        .CLKOS_DIV(60),
+        .CLKOS_CPHASE(5),
+        .CLKOS_FPHASE(0),
+        .FEEDBK_PATH("CLKOP"),
+        .CLKFB_DIV(2)
+    ) pll_i (
+        .RST(1'b0),
+        .STDBY(1'b0),
+        .CLKI(clkin),
+        .CLKOP(clkout0),
+        .CLKOS(clkout1),
+        .CLKFB(clkout0),
+        .CLKINTFB(),
+        .PHASESEL0(1'b0),
+        .PHASESEL1(1'b0),
+        .PHASEDIR(1'b1),
+        .PHASESTEP(1'b1),
+        .PHASELOADREG(1'b1),
+        .PLLWAKESYNC(1'b0),
+        .ENCLKOP(1'b0),
+        .LOCK(locked)
+	);
+endmodule

hardware/colorlight-base/README.md

@@ -1,3 +1,17 @@
 # Manufacturing specs
 
-Designed for JLC7628 stackup.
+Designed for JLC7628 stackup.
+
+# Revision Notes
+
+## Revision A
+
+- Missing silkscreen labels for debug headers and UART headers
+- Pogo pins not *quite* centered.
+- Pogo pins should export 4 parts, not 1.
+- Power regulator and ADC should be moved to underside of board to avoid potential mechanical conflicts.
+- Ethernet magnetics footprint is incorrect (too slim).
+- Should have some way to provide power for standalone debugging (USB?)
+- I2C should have DNP pullup resistor footprints
+- Reset and/or power button would be nice
+- Pads on DDR connector could be thinned slightly