41 lines
2.2 KiB
Markdown
41 lines
2.2 KiB
Markdown
# Sampler clock design and CDC considerations
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Essentially, I have to support two clock domains, one for the ADC sampling
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itself and one for system clock, otherwise we'll have issues pushing the
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bandwidth we need to export the data.
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Sampling speed will be 10MHz, as limited by memory resources. Ideally the system
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clock will be 50MHz, but 40MHz is a decent minimum IMO.
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The sampler module itself will operate on system clock, with a wishbone
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interface. It will pass the sample clock into smaller sub-modules that read the
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data from the ADCs. (TODO I need to figure out how to deal with how exactly to
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sample the data pins relative to the clock, make sure the signal is stable when
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I clock it in. Maybe do negative edge? Idk.)
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- Control signals to the ADC (DFS, 3-STATE, REFSENSE), will be directly wired to
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control registers.
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- STBY will be controlled by the sampler module
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- OTR will be synchronized in to sysclk with n-FF, it is clocked to 10MHz domain
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An enable signal will be synchronized in to the sample clock domain, and that
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will be used by the sampler submodules to pull STBY high, and begin sampling.
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The sampling submodules will be very dumb, and export the data as determined by
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the enable signal, (i.e. wait 5 clocks to start/stop to manage ADC pipeline
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latency).
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The data will be synchronized straight through, data connected comb, and a
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toggled pin to synchronize the data into sysclk. We can export at full speed if
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we latch data in on a change in the toggle pin instead of setting high and
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waiting for it to go low. (Otherwise we need to implement some sort of gearing
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to push multiple samples through every few sample clocks.) This is okay for CDC
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because sysclk is faster than sample clock, so any transition will last long
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enough to propogate through the synchronizers, and when we get a change through
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the synchronyzer, we can know that the data is valid. This assumes sysclk is at
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least 4x faster than the sample clock, so the toggle pin can propogate through
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the synchronizer, and the data is still valid before the next sample clock edge.
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On the sysclk side, the toggle will turn into a strobe and data will feed into
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circular buffers to store the ping data. It will also be exported to the peak
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detector module.
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