127 lines
5.1 KiB
Markdown
127 lines
5.1 KiB
Markdown
# Sampling Module Design Datasheet
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TODO this should be generated by the gateware build infrastructure
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TODO there is also potential to make samples 9 bits, which would take the same
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number of EBR resources as 8 bits, it would make the packets larger, but I don't
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think that's a major concern. I am thinking we should do 9 bits. It won't slow
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down any of our operations, as it goes from byte sized loads to half word loads,
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which are all single instructions anyways
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## Operation
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When the ADCs are enabled (via CCR->ENABLE), then the data FIFOs are
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continuously updated with incoming samples. The user can start (CCR->START)
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a new capture, which primes the block to save the appropriate samples.
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A capture does not happen until it is triggered, which can be done either
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automatically (iff CCR->AUTO_TRG_EN is set to 1), or via manual software trigger
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(via CCR->TRIGGER). The samples are configured with 2 parameters: CAP_OFFSET, and CAP_LEN.
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CAP_OFFSET determines how many samples prior to the trigger will be saved, and CAP_LEN
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determines the total number of samples to save.
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The sample received on the clock that the trigger will be the (0-indexed) CAP_OFFSET'th sample
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in the total capture. (TODO better description for that)
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*Note: a capture can not be triggered unless the SR->READY flag is set. The READY
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flag is set by the following logic: `CCR->ENABLE && CCR->START && samples_saved >= CACHED_CAP_OFFSET`.*
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### Automatic Triggering and Peak Detection
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Each acquisition unit has its own peak detector in. This measures the difference
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between the maximum and minimum values read within 3/4 of a cycle. The time of a
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cycle is determined by the frequency set via CCR->FREQ. This value can be read
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via PP_VALUE_X (X being the ADC number).
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This value can be manually read by software for each channel to do gain
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adjustments or peak detection in software if wanted, however this value can also
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be used to trigger automatically. The automatic trigger occurs as soon as this value
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is greater than or equal to the value set in CCR->PP_THRESH.
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### Interrupts
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An external interrupt will be sent to the CPU by this module for both the
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trigger event and the acquisition complete event. It will be two different
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lines, maskable by the RISCV mie CSR. TBD is how to reset them or if that needs
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to happen or whatever.
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## Registers
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32 bits unless specified otherwise. Fields not specified will always read 0 and writes will do nothing
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Shared across all acquisition blocks, except for PP_VALUE_X, and DATA_X which both have one register per ADC.
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### CCR (R/W)
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Configuration and Control Register
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Default value: 0 for all fields
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| Field | Bit Width | Description |
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|----------------|-----------|-------------|
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| ENABLE | 1 | Enables/Disables the ADC itself. Also starts pulling data into FIFO |
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| START | 1 | Set this bit to prime a capture. Locks in all offset and frequency settings (sets when not enabled and ready will do nothing, sets with an ongoing trigger re-load new settings, start trigger anew, clear to stop capture), value when read will be if a trigger is active |
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| TRIGGER | 1 | Manually trigger a capture. Will always read 0 |
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| AUTO_TRG_EN | 1 | Enables
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| FREQ | 2 | Sets the frequency the ping detector submodule uses. (See FREQ_ENUM) |
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| PP_THRESH | 10 | Full scale peak to peak threshold to auto trigger a capture. |
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FREQ_ENUM:
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- 0b00: 25kHz
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- 0b01: 30kHz
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- 0b10: 35kHz
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- 0b11: 40kHz
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### SR (R/O)
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Status Register
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This will have 4 sets of fields of status bits, one per ADC
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| Field | Bit Width | Description |
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|----------------|-----------|-------------|
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| READY | 1 | FIFO has acquired enough samples to hold requested history. |
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| TRIGGERED | 1 | Capture has been triggered. Cleared on next START |
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| COMPLETE | 1 | Capture is finished, cleared on next START |
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| TBD status bits| TBD | Any status lines we get from the ADC will be exported here |
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### CAP_OFFSET
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32-bit field that determines how many samples to acquire from before the trigger. Must be < CAP_LEN - 10
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(max value enforced by hardware)
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### CAP_LEN
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32-bit field that determines how many samples total to acquire for the whole trigger. Must be < size of FIFO
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(max size enforced by hardware)
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### PP_VALUE_X
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One register per acquisition block
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10-bit field with the highest measured peak-to-peak values
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Write anything to reset to 0
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Gets reset to 0 when a new capture is started (note: not when it is triggered)
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### DATA_X
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8-bit register (otherwise just 0s), returns the top 8 bits of each sample.
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(maybe not the top, depending on scale/range, but that can be changed later).
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All other bits are 0.
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Reading this register before a trigger occurs is invalid.
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Reading a byte consumes the byte from the FIFO, user is expected to track the correct
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number of bytes to read, reading over the end of the FIFO is invalid.
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All invalid reads return 0. (Real data should never be 0, so this is a good indicator.)
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## Interrupts
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Since all of these should have the same timing offsets, these interrupts are common to all acquisition blocks.
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Trigger
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Capture complete
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