803 lines
31 KiB
Plaintext
803 lines
31 KiB
Plaintext
(kicad_sch (version 20230121) (generator eeschema)
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(text "2.9mm from base of board to bottom (3.4mm - 1mm/2) for my ddr2 connectors\nthis roughly matches measurement"
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(at 158.75 72.39 0)
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(effects (font (size 1.27 1.27)) (justify left bottom))
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(uuid 087e6424-5b70-4c26-b70f-6064dc72f9b3)
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(text "So pogo pins are 24.6mm away from left edge of shielding pad"
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(at 156.21 113.03 0)
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(text "edge is 19mm from farthest metal bit on mount" (at 156.21 100.33 0)
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|
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(text "pogo pins are 11.4m in from the top edge" (at 156.21 115.57 0)
|
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(uuid 72ce604b-3998-4f91-a7a1-fb04080ab9b1)
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|
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(text "Softcore JTAG connector" (at 50.8 102.87 0)
|
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|
|
(uuid 78f15713-9aac-4cdd-a164-b94ae5cd06dd)
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|
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(text "On the dev board, the bottom of the board is ~2mm from the base board (if the pogo pins weren't mounted, i.e. pressed down)\n"
|
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(at 158.75 67.31 0)
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(text "First one is 9.4mm from edge\n" (at 157.48 95.25 0)
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(text "Pogo holes ~2mm from edge of colorlight\n" (at 154.94 91.44 0)
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(uuid b2c38e41-9a7c-4b2b-81de-b20fc7be1620)
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(text "39.3 from edge of colorlight to back edge of plastic"
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(uuid ba4da3ea-b8b6-4262-bc88-ae63685ac95c)
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(text "These JTAG signals can be routed to arbitrary pads on\nthe FPGA."
|
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(at 78.74 140.97 0)
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(uuid bc7d7bf9-d2e1-4a6a-bfdf-a2422845eeeb)
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(text "That protrusion is 21.45-13.85mm from the left edge of the DDR2 connector"
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(at 153.67 107.95 0)
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(uuid bca4706e-c4a8-4e38-bbf4-7e3db24ab4a3)
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(text "Debug header:\nI need JTAG specifically and the\neasy options (f103, or ft2232h)\nwere out of stock, so I'll just use\nan external interface.\n\nMore flexible anyways."
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(at 57.15 38.1 0)
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(text "Extra port for if I need to break wires out." (at 106.68 49.53 0)
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