David Lenfesty 0bf4fb5c1b gateware: test out UART, had to fix SR flags		2023-02-04 14:40:05 -07:00
..
amaranth-boards@1d82f2ece1	gateware: first attempt at amaranth SoC	2023-01-21 22:43:17 -07:00
docs	gateware: start some design documentation and clarify some design	2023-01-22 20:15:48 -07:00
.gitignore	gateware: create vcd_out directory by default	2023-01-29 20:41:17 -07:00
design_notes.md	Improve top-level docs	2023-01-23 22:27:45 -07:00
env.bash	gateware: made basic SoC, mostly just copying existing colorlight target	2023-01-06 19:03:46 -07:00
i2c.py	gateware: saving some WIP on UART	2023-02-04 12:04:01 -07:00
led.py	gateware: fix some issues introduced with cleanup	2023-01-29 16:54:14 -07:00
main.py	gateware: saving some WIP on UART	2023-02-04 12:04:01 -07:00
memory.py	gateware: start spreading out into a couple modules	2023-01-23 22:32:46 -07:00
minerva_notes.md	Improve top-level docs	2023-01-23 22:27:45 -07:00
test_i2c.py	gateware: test out UART, had to fix SR flags	2023-02-04 14:40:05 -07:00
test_uart.py	gateware: test out UART, had to fix SR flags	2023-02-04 14:40:05 -07:00
tests.py	gateware: test out UART, had to fix SR flags	2023-02-04 14:40:05 -07:00
uart.py	gateware: test out UART, had to fix SR flags	2023-02-04 14:40:05 -07:00