1.1 KiB
Acquisition capture design
How much data do we need to capture worst case?
- 2ms @ 40MHz
80_000 samples, or 160_000 bytes (if we assume >8 bit samples)
LFE5U-45 has 108 18kbit sysMEM blocks.
18kbit is roughly equal to 2kB, so 80 EBR blocks per channel
shit
DDR2 provides up to 800Mbit/s data rates
800 / 40MHz = 20 bits, not enough to stream data out either...
huh
This may be problematic
if we chop to 20MHz and 1 byte per sample, we get 40_000 bytes per channel
This puts us at 20 EBR blocks per channel, which is feasible, 28 EBR to use for other resources
Huh, this is very marginal. Maybe should have gone with something else.
Oh well
Likely the best thing to do here, is to add icache and dcache, and put system memory behind DRAM.
And also pull code in to DRAM
Interfaces to support:
DAC for setting gain. (DAC needs to be added in hardware)
I2C to set Variable Oscillator for setting filter frequencies
Peak detector does not have an ADC on board. Given this, we should just do peak detection in gateware.
General notes
Will need to have a timer implemented as well