79 lines
3.1 KiB
Markdown
79 lines
3.1 KiB
Markdown
# Updated Sonar System
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This repository contains all the design files for my attempt at an updated and
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improved passive sonar data acquisition system. The goal of this system is
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simply to be able to capture pinger data, filtered by the preprocessor board,
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via ethernet, at significantly faster speed than the previous system.
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## Repo Layout
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```
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firmware/
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hello_world_c - My very first testing code for doing SoC bringup
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TODO - break FW out into multiple crates to provide more functionality
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gateware/ - RTL for creating the SoC
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hardware/ - Directory for any hardware designs
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pmod/ - A PMOD interface board, using 4 ADCs with LVDS converters to get data across PMOD [Failed Idea]
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colorlight-base/ - Baseboard that attaches to the preprocessor (replases BeagleBone + PruDAQ)
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sonar-footprints.pretty/ - custom KiCAD footprints for this project
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sonar_symbols.kicad_sym - custom KiCAD symbols I create for hardware
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colorlight_pin_extractor.py - a script I used to help in making the kicad symbol for the colorlight module
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```
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## Design Goals
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- ~~4x 20MSPS channels @ > 8 bits~~ Reduced to 10MSPS @ 9 bits due to memory resource constraints.
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- Ethernet data channel
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- Simplified software stack (or at least fewer layers of components)
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- Well-documented
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## RTL Architecture
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General SoC architecture and other similar goodies can be found in
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`gateware/docs`.
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To over simplify, I am creating an SoC with an rv32im core, connected to a
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single wishbone bus to access all memory and peripherals. All RTL is written in
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Amaranth.
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## Firmware Architecture
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Given how much I can very simply offload onto the RTL (peak detection, maaaybe DMA, etc.),
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the firmware will be pretty simple. I will use embassy just to make things easier
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on myself. All I really have to do is provide some configuration interface over ethernet,
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set up and read out captures, and push those to the Xavier.
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The configuration interface only needs to expose the following functionality:
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- Stop/start capturing
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- Set filter frequency
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- Set capture size and offset
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- Automatic triggering settings
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- Manual triggering
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The data channel can be whatever form I want, although if ZMQ is easy to
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implement I may keep it to reduce changes to the ROS software.
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## Random notes
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You will probably need to un write-protect the flash on the colorlight
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Will *not* be doing LVDS system, because arty doesn't have selectable bank
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voltage to actually use it.
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Switching to use Colorlight i9 board (ECP5 UP5K 45), because it has plenty IO
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broken out, also provides ethernet (I just need to implement the magnetics and
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jack), and is cheaper/potentially easier to acquire for ARVP in the future. The
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LiteX implementation fits in <40% of total resources of the 25K LUT variant, so
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the 45K should be plenty for what I need. Frankly what I'm implementing is very
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simple. It can probably even handle doing the FFT on board if I wanted to.
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### ecpdap: "Error: specified probe not found"
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A Reboot fixed it....
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Do I have ecpdap installed in two places and one of them doesn't work maybe?
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I do have two versions installed. one from oss-cad-suite and one by building it
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manually.
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