| .. |
|
amaranth-boards@1d82f2ece1
|
gateware: first attempt at amaranth SoC
|
2023-01-21 22:43:17 -07:00 |
|
docs
|
gateware: saving some state again
|
2023-02-18 11:56:39 -07:00 |
|
liteeth
|
gateware: saving some state again
|
2023-02-18 11:56:39 -07:00 |
|
.gitignore
|
gateware: create vcd_out directory by default
|
2023-01-29 20:41:17 -07:00 |
|
design_notes.md
|
Improve top-level docs
|
2023-01-23 22:27:45 -07:00 |
|
env.bash
|
gateware: made basic SoC, mostly just copying existing colorlight target
|
2023-01-06 19:03:46 -07:00 |
|
eth.py
|
gateware: actually integrate ethernet
|
2023-03-04 10:54:43 -07:00 |
|
gen_liteeth.sh
|
gateware: saving some state again
|
2023-02-18 11:56:39 -07:00 |
|
gen_pll.sh
|
gateware: generate PLL with 'ecppll'
|
2023-02-25 12:24:03 -07:00 |
|
i2c.py
|
gateware: saving some WIP on UART
|
2023-02-04 12:04:01 -07:00 |
|
led.py
|
gateware: fix some issues introduced with cleanup
|
2023-01-29 16:54:14 -07:00 |
|
liteeth_config.yaml
|
gateware: import basic instance of LiteEth
|
2023-02-07 21:00:38 -07:00 |
|
main.py
|
gateware: actually integrate ethernet
|
2023-03-04 10:54:43 -07:00 |
|
memory.py
|
gateware: start spreading out into a couple modules
|
2023-01-23 22:32:46 -07:00 |
|
minerva_notes.md
|
Improve top-level docs
|
2023-01-23 22:27:45 -07:00 |
|
pll.v
|
gateware: generate PLL with 'ecppll'
|
2023-02-25 12:24:03 -07:00 |
|
test_i2c.py
|
gateware: test out UART, had to fix SR flags
|
2023-02-04 14:40:05 -07:00 |
|
test_uart.py
|
gateware: test out UART, had to fix SR flags
|
2023-02-04 14:40:05 -07:00 |
|
test.gtwk
|
gateware: saving some state again
|
2023-02-18 11:56:39 -07:00 |
|
tests.py
|
gateware: test out UART, had to fix SR flags
|
2023-02-04 14:40:05 -07:00 |
|
uart.py
|
gateware: test out UART, had to fix SR flags
|
2023-02-04 14:40:05 -07:00 |
