David Lenfesty
8d00e15835
Bus widths should now all be correct. (addresses and sizes in amaranth take into account the granularity selection, so granularity acts like two extra bits on the bus address line) Also don't ignore a warning about undriven resets. Turns out that can gate *everything* off in your design.
210 lines
7.5 KiB
Python
210 lines
7.5 KiB
Python
#!/usr/bin/env python3
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from amaranth import *
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from amaranth.sim import *
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from amaranth_boards import colorlight_i9
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from amaranth_soc.wishbone import *
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from minerva.core import Minerva
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from typing import List
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from argparse import ArgumentParser
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from pathlib import Path
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import unittest
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import sys
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import os
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from memory import *
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from led import *
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from eth import *
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import i2c
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import test_i2c
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import uart
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# To change clock domain of a module:
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# new_thing = DomainRenamer("new_clock")(MyElaboratable())
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# TODO clean this up, generate binary here, maybe even run cargo build
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def load_firmware_for_mem() -> List[int]:
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with open('../firmware/fw.bin', 'rb') as f:
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# Stored as little endian, LSB first??
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data = f.read()
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out = []
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assert(len(data) % 4 == 0)
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for i in range(int(len(data) / 4)):
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out.append(int.from_bytes(data[i*4:i*4+4], byteorder='little'))
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return out
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class Core(Elaboratable):
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def __init__(self, clk25, led_signal, eth_interface):
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self.count = Signal(64)
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self.cpu = Minerva(reset_address=0x01000000, with_debug=False)
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self.arbiter = Arbiter(addr_width=30, data_width=32, granularity=8)
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self.decoder = Decoder(addr_width=30, data_width=32, granularity=8, features=["err"])
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self.clk25 = clk25
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self.led_signal = led_signal
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self.eth_interface = eth_interface
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def elaborate(self, platform):
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m = Module()
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m.submodules.cpu = self.cpu
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m.submodules.arbiter = self.arbiter
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m.submodules.decoder = self.decoder
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# Create main and sampling clock, using PLL and 25MHz input clock
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if platform is not None:
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platform.add_file("pll.v", open("pll.v", "r").read())
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sys_clk = Signal()
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sample_clk = Signal()
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pll = Instance(
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"pll",
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i_clkin=self.clk25,
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o_clkout0=sys_clk,
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o_clkout1=sample_clk,
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)
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m.submodules.pll = pll
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# Create new clock domains
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m.domains += ClockDomain("sync")
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m.domains += ClockDomain("sample")
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m.d.comb += ClockSignal("sync").eq(sys_clk)
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m.d.comb += ClockSignal("sample").eq(sample_clk)
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# Add clock constraints
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if platform is not None:
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platform.add_clock_constraint(sys_clk, 50e6)
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platform.add_clock_constraint(sample_clk, 10e6)
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# Connect ibus and dbus together for simplicity for now
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minerva_wb_features = ["cti", "bte", "err"]
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self.ibus = Interface(addr_width=30, data_width=32, granularity=8, features=minerva_wb_features)
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# Note this is a set of statements! without assigning to the comb domain, this will do nothing
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m.d.comb += self.cpu.ibus.connect(self.ibus)
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self.arbiter.add(self.ibus)
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self.dbus = Interface(addr_width=30, data_width=32, granularity=8, features=minerva_wb_features)
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m.d.comb += self.cpu.dbus.connect(self.dbus) # Don't use .eq, use .connect, which will appropriately assign signals
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# using .eq() gave me Multiple Driven errors
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self.arbiter.add(self.dbus)
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# TODO do something with interrupts
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# These are interrupts headed into the CPU
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self.interrupts = Signal(32)
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m.d.comb += [
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# Used for mtime registers, which are memory-mapped (not CSR), so I would have to implement.
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# If I cared.
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self.cpu.timer_interrupt.eq(0),
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# Ostensibly exposed to us so we can interrupt one hart (CPU in this context) from another, we don't need this.
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self.cpu.software_interrupt.eq(0),
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# External interrupt lines, would be for any interrupts I implemented w/ a custom interrupt controller.
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# Most likely I'll map a few lines to some peripherals, won't do anything fancy
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self.cpu.external_interrupt.eq(self.interrupts),
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]
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fw = load_firmware_for_mem()
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# Hook up memory space
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self.rom = ROM(fw)
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m.submodules.rom = self.rom
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# Problem: not sure to handle how we do byte vs word addressing properly
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# So doing this shift is a bit of a hacky way to impl anything
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start, _stop, _step = self.decoder.add(self.rom, addr=0x01000000)
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print(f"ROM added at 0x{start:08x}")
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self.ram = RAM()
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m.submodules.ram = self.ram
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start, _stop, _step = self.decoder.add(self.ram)
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print(f"RAM added at 0x{start:08x}")
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self.led = LEDPeripheral(self.led_signal)
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m.submodules.led = self.led
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start, _stop, _step = self.decoder.add(self.led)
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print(f"LED added at 0x{start:08x}")
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m.submodules.uart = uart.UART(10e6)
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# Ethernet
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self.eth = LiteEth(self.eth_interface)
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m.submodules.eth = self.eth
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start, _stop, _step = self.decoder.add(self.eth, addr=0x02000000)
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print(f"LiteETH added at 0x{start:08x}")
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# Connect arbiter to decoder
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m.d.comb += self.arbiter.bus.connect(self.decoder.bus)
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# Counter
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#m.d.sync += self.count.eq(self.count + 1)
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#with m.If(self.count >= 50000000):
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# m.d.sync += self.count.eq(0)
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# m.d.sync += led.eq(~led)
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return m
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class SoC(Elaboratable):
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def __init__(self):
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pass
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def elaborate(self, platform):
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if platform is not None:
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clk25 = platform.request("clk25")
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led_signal = platform.request("led")
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ethernet_interface = platform.request("eth_rgmii", 1)
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else:
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# platform is None in simulation, so provide harnesses for required signals
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clk25 = Signal() # TODO unsure if this will work in sim
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led_signal = Signal()
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ethernet_interface = Record(rgmii_layout)
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return Core(clk25, led_signal, ethernet_interface)
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# TODO add structure to add regression tests
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def run_sim():
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dut = SoC()
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sim = Simulator(dut)
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def proc():
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for i in range(1000):
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yield Tick()
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sim.add_clock(1e-6)
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sim.add_sync_process(proc)
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with sim.write_vcd('sim.vcd', gtkw_file='sim.gtkw'):
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sim.reset()
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sim.run()
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if __name__ == "__main__":
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args = ArgumentParser(description="ARVP Sonar Acquisition FPGA gateware.")
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args.add_argument("--build", action="store_true", help="Build bitstream.")
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args.add_argument("--gen-debug-verilog", action="store_true", help="Save debug verilog.")
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# TODO maybe allow an optional arg to specify an individual test to run?
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args.add_argument("--test", action="store_true", help="Run RTL test suite and report results.")
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args.add_argument("--save-vcd", action="store_true", help="Save VCD waveforms from test(s).")
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args.add_argument("--sim", action="store_true", help="Run overall simulation")
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args = args.parse_args()
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if args.build:
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# Overrides are available via AMARANTH_<override_variable_name> env variable, or kwarg
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# TODO fix platform so I don't have to manually specify MDIO signal
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colorlight_i9.Colorlight_i9_Platform().build(SoC(), debug_verilog=args.gen_debug_verilog, nextpnr_opts="--router router1", add_preferences="LOCATE COMP \"top.eth.core.rgmii_eth_mdio\" SITE \"P5\";\n")
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if args.test:
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if args.save_vcd:
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if not Path("vcd_out").exists():
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os.mkdir("vcd_out")
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os.environ["TEST_SAVE_VCD"] = "YES"
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# Super hacky... why am I doing this
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test_modules = [mod for mod in sys.modules if mod.startswith("test_")]
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for mod in test_modules:
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unittest.main(module=mod, argv=[sys.argv[0]])
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if args.sim:
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run_sim()
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