Commit Graph

13 Commits

Author SHA1 Message Date
8d00e15835 gateware: fix dumb mistakes
Bus widths should now all be correct. (addresses and sizes in amaranth
take into account the granularity selection, so granularity acts like
two extra bits on the bus address line)

Also don't ignore a warning about undriven resets. Turns out that can
gate *everything* off in your design.
2023-03-05 11:43:59 -07:00
8b19464608 gateware: propogate MDIO signal correctly w/o IOBUF
This was causing my nextpnr crash. I really do need to figure out how to
do this in a less hacky way. Or even just make it more explicit that I
am doing this for a reason.
2023-03-04 12:41:16 -07:00
6e89c0d837 gateware: actually integrate ethernet 2023-03-04 10:54:43 -07:00
56d13a0e77 gateware: add PLL and generate two clocks
TODO is make a proper clock gen object, maybe it could run ecppll by
itself?
2023-02-25 12:56:09 -07:00
fe379be39b gateware: saving some state again 2023-02-18 11:56:39 -07:00
52012dc4ad gateware: saving some WIP on UART 2023-02-04 12:04:01 -07:00
9997db0ac8 gateware: create vcd_out directory by default 2023-01-29 20:41:17 -07:00
ad3be1f4c7 gateware: put in some testing infrastructure
It's pretty hacky tbh, probably should be improved.

But also this will probably scale with the entire project so I don't
care.
2023-01-29 20:38:32 -07:00
6a4a9784e3 gateware: fix some issues introduced with cleanup 2023-01-29 16:54:14 -07:00
5619482029 gateware: start spreading out into a couple modules 2023-01-23 22:32:46 -07:00
296206524c gateware: remove LiteX attempt 2023-01-23 22:28:03 -07:00
a6673297d4 gateware: failed attempt to add my own peripheral to litex
moving to amaranth because it at least has API docs :(
2023-01-10 20:30:00 -07:00
356ffb4e98 gateware: made basic SoC, mostly just copying existing colorlight target 2023-01-06 19:03:46 -07:00