Had too many issues with integrating LiteEth. I put my FW into a LiteX SoC and it worked, so I migrated back. With the knowledge I gained doing Amaranth I could fix the issues I had adding a wishbone slave device pretty easily.
29 lines
1.2 KiB
Python
29 lines
1.2 KiB
Python
from migen import *
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from litex.soc.interconnect.wishbone import *
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from litex.soc.integration.soc import SoCRegion
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class Sampler(Module):
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def __init__(self, adc_pins):
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# TODO correct addr width
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self.bus = Interface(data_width=32, adr_width=11)
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# self.clock_domains.foo = ClockDomain() is how to add a new clock domain, accessible at self.foo
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# Provide a slow clock to the ADC, 60MHz / 600 = 100kHz
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self._counter = Signal(32)
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self.sync += self._counter.eq(self._counter + 1)
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self.sync += If(self._counter >= 600, self._counter.eq(0), adc_pins.refclk.eq(~adc_pins.refclk))
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# Set config pins to constant values
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self.comb += adc_pins.oen_b.eq(0) # Data pins enable
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self.comb += adc_pins.standby.eq(0) # Sampling standby
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self.comb += adc_pins.dfs.eq(0) # DFS (raw or two's complement)
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# The only remaining pin, OTR, is an out of range status indicator
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# Read directly from the data pins into the wishbone bus for now, just for bringup
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self.comb += self.bus.dat_r.eq(adc_pins.data)
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self.sync += self.bus.ack.eq(0)
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self.sync += If(self.bus.cyc & self.bus.stb, self.bus.ack.eq(1))
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