..
docs
gateware: saving some state again
2023-02-18 11:56:39 -07:00
jtagtap @ 851b71bb8b
add jtagdap submodule for now
2023-03-05 11:52:16 -07:00
liteeth
gw: get LiteEth working!
2023-04-15 18:11:16 -06:00
platforms
gateware: move back to LiteX
2023-04-22 18:35:13 -06:00
.gitignore
gateware: create vcd_out directory by default
2023-01-29 20:41:17 -07:00
design_notes.md
Improve top-level docs
2023-01-23 22:27:45 -07:00
env.bash
gateware: made basic SoC, mostly just copying existing colorlight target
2023-01-06 19:03:46 -07:00
eth.py
gw: get LiteEth working!
2023-04-15 18:11:16 -06:00
gen_liteeth.sh
gateware: saving some state again
2023-02-18 11:56:39 -07:00
gen_pll.sh
gateware: generate PLL with 'ecppll'
2023-02-25 12:24:03 -07:00
i2c.py
gateware: make i2c actually read status bits
2023-03-25 15:21:35 -06:00
led.py
gateware: fix dumb mistakes
2023-03-05 11:43:59 -07:00
liteeth_config.yaml
gateware: import basic instance of LiteEth
2023-02-07 21:00:38 -07:00
litex_main.py
gateware: move back to LiteX
2023-04-22 18:35:13 -06:00
main.py
gw: get LiteEth working!
2023-04-15 18:11:16 -06:00
memory.py
gateware: fix RAM and ROM issues
2023-03-25 15:21:03 -06:00
minerva_notes.md
Improve top-level docs
2023-01-23 22:27:45 -07:00
pll.v
gateware: generate PLL with 'ecppll'
2023-02-25 12:24:03 -07:00
sampler.py
gateware: move back to LiteX
2023-04-22 18:35:13 -06:00
test_i2c.py
gateware: test out UART, had to fix SR flags
2023-02-04 14:40:05 -07:00
test_uart.py
gateware: test out UART, had to fix SR flags
2023-02-04 14:40:05 -07:00
test.gtwk
gateware: saving some state again
2023-02-18 11:56:39 -07:00
tests.py
gateware: test out UART, had to fix SR flags
2023-02-04 14:40:05 -07:00
timer.py
tracking a couple files I missed
2023-04-16 11:06:02 -06:00
uart.py
gateware: add UART to CSR
2023-03-24 17:42:27 -06:00