46 lines
1.1 KiB
Markdown
46 lines
1.1 KiB
Markdown
# Acquisition capture design
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How much data do we need to capture worst case?
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- 2ms @ 40MHz
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80_000 samples, or 160_000 bytes (if we assume >8 bit samples)
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LFE5U-45 has 108 18kbit sysMEM blocks.
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18kbit is roughly equal to 2kB, so 80 EBR blocks per channel
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shit
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DDR2 provides up to 800Mbit/s data rates
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800 / 40MHz = 20 bits, not enough to stream data out either...
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huh
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This may be problematic
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if we chop to 20MHz and 1 byte per sample, we get 40_000 bytes per channel
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This puts us at 20 EBR blocks per channel, which is feasible, 28 EBR to use for other resources
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Huh, this is *very* marginal. Maybe should have gone with something else.
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Oh well
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Likely the best thing to do here, is to add icache and dcache, and put system memory behind DRAM.
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And also pull code in to DRAM
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# Interfaces to support:
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DAC for setting gain. (DAC needs to be added in hardware)
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I2C to set Variable Oscillator for setting filter frequencies
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Peak detector does not have an ADC on board. Given this, we should just do peak detection in gateware.
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# General notes
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Will need to have a timer implemented as well |