66 lines
1.6 KiB
Markdown
66 lines
1.6 KiB
Markdown
# Building Instructions
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All of this is assumed to be on a linux system. Eventually I'll probably make or
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use some dockerfile or nix flake that has all this installed already.
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## Toolchain Installation
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### Trellis and FPGA toolchain
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First, get an [oss-cad-suite release](https://github.com/YosysHQ/oss-cad-suite-build/releases),
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and unpack it into an install directory of your choice.
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Ensure the `bin/` folder is included in your build environment's PATH.
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### Rust
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Install the rust toolchain with the instructions at [rustup.rs](https://rustup.rs).
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Install the RV32 target:
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```shell
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rustup target add riscv32i-unknown-none-elf
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```
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### ecpdap (Optional?)
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You may or may not have to install your own version of ecpdap, I found the one
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in `oss-cad-suite` didn't work for whatever reason, so I had to install it
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myself. There are releases on the github, or you can just build it yourself with
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Rust. Just make sure you either replace the binary in the oss-cad-suite location
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or make sure this version of ecpdap has priority in PATH.
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## Building
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TODO is to unify everything into a top-level python script, but until then, you have to live with this.
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Firmware must be built first, as it gets incorporated into RTL image.
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Firmware can be built with:
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```shell
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cd firmware/
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cargo build --release
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```
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Gateware can be built with:
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```shell
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cd gateware/
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python3 soc.py --build
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```
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## Programming
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Gateware can be programmed to the FPGA in volatile memory with:
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```shell
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ecpdap program gateware/build/top.bit --freq 10M
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```
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Gateware can be written to flash with:
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```shell
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# TODO, it's a lightly awkward command that isn't in my shell history
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```
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