2.2 KiB
Sampler clock design and CDC considerations
Essentially, I have to support two clock domains, one for the ADC sampling itself and one for system clock, otherwise we'll have issues pushing the bandwidth we need to export the data.
Sampling speed will be 10MHz, as limited by memory resources. Ideally the system clock will be 50MHz, but 40MHz is a decent minimum IMO.
The sampler module itself will operate on system clock, with a wishbone interface. It will pass the sample clock into smaller sub-modules that read the data from the ADCs. (TODO I need to figure out how to deal with how exactly to sample the data pins relative to the clock, make sure the signal is stable when I clock it in. Maybe do negative edge? Idk.)
- Control signals to the ADC (DFS, 3-STATE, REFSENSE), will be directly wired to control registers.
- STBY will be controlled by the sampler module
- OTR will be synchronized in to sysclk with n-FF, it is clocked to 10MHz domain
An enable signal will be synchronized in to the sample clock domain, and that will be used by the sampler submodules to pull STBY high, and begin sampling. The sampling submodules will be very dumb, and export the data as determined by the enable signal, (i.e. wait 5 clocks to start/stop to manage ADC pipeline latency).
The data will be synchronized straight through, data connected comb, and a toggled pin to synchronize the data into sysclk. We can export at full speed if we latch data in on a change in the toggle pin instead of setting high and waiting for it to go low. (Otherwise we need to implement some sort of gearing to push multiple samples through every few sample clocks.) This is okay for CDC because sysclk is faster than sample clock, so any transition will last long enough to propogate through the synchronizers, and when we get a change through the synchronyzer, we can know that the data is valid. This assumes sysclk is at least 4x faster than the sample clock, so the toggle pin can propogate through the synchronizer, and the data is still valid before the next sample clock edge.
On the sysclk side, the toggle will turn into a strobe and data will feed into circular buffers to store the ping data. It will also be exported to the peak detector module.