73 lines
2.4 KiB
Markdown
73 lines
2.4 KiB
Markdown
# Updated Sonar System
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## Repo Layout
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```
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hardware/ - Directory for any hardware designs
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pmod/ - A PMOD interface board, using 4 ADCs with LVDS converters to get data across PMOD
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```
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## Design Goals
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- 4x 20MSPS channels @ > 8 bits
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- Ethernet data channel
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- Simplified software stack (or at least fewer layers of components)
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- Well-documented
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## System Architecture
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<!-- made with asciiflow.com -->
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```
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┌─────────────┐
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│Main Computer│
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└─────▲───────┘
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│
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│
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│
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┌─────┴──────┐
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│Ethernet PHY│
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│ ▲ │ Interface Board (x4)
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│ │ │ ┌──────────────────────────────┐
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│ │ │ │ │ ┌─────────────┐
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│ │ │◄──────┤ LVDS Serializer◄─────────ADC │◄───────────┤ Hydrophones │
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│ │ │ │ │ └─────────────┘
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│ │ │ └──────────────────────────────┘
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│ FPGA │
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└─────▲──────┘
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│ Dev Board
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│ or
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│ Custom Board
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│
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│
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│
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┌──┴───────────────────┐
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│ Peak Detector Board │
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└──────────────────────┘
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(Temporary)
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```
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## RTL Architecture
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#### Diagram TODO
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The plan is to use LiteX and let it do most of the heavy lifting. Components to
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generate:
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- Softcore (some RISC-V core)
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- Main memory bus
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- DMA engine
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- Gigabit Ethernet MAC
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THis way the only actual RTL to write is the peripheral that interacts with the ADCs,
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which should be very simple. To do early bringup I can start with a blinky peripheral to
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demonstrate access to the bus, and then I can keep adding functionality.
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## Software Planning
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Will try to use embassy on RISC-V if I can.
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Should make sure to have a debug port available as early as possible.
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I will make the interface as generic as possible, so it should be easy to swap out, but I
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will start by targetting zmq so I can change as little of the software stack as possible.
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